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The Xilinx XC9500XL series is a popular CPLD series. It's 5V-tolerance, relatively low price, and many I/O pins make it a good choice for many projects.
IMO, this would be a good candiate for a new…
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I am trying boot Barge OS on PYNQ-Z1(Xilinx ZYNQ).
I got a kernel panic.
```
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2)
```
I tried with SD cards of so…
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I got new TE0712 modules. On a working setup, I replaced an old programmed modules with the new module. I could load the bitfile to FPGA, and the board worked as expected until reboot/repower. Then …
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### Problem Description
I'm currently interested in p2p data transfer from FPGA (Xilinx Alveo U50) to an AMDGPU. There are already implementation for FPGA-Nvidia GPU at https://github.com/RC4ML/FpgaN…
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The XIlinx ZCU102 board has a good support for Xen and works well with Zephyr and Linux.
The main two drawbacks are the price and the missing virtualization support for the GPU.
The idea is to fin…
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This is a feature request for adding support to parse major vendor extensions (Xilinx) to ipyxact.
Below is an example of a fileSet extension that specifies a dependency between a Xilinx core to a …
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Hi all, our lab has only a soc xilinx zcu102 and i'm a freshman of FPGA developing. I want to verify zynqnet on zcu102 so i have to transplant it from 7045 to zcu102. Are there any docs or other proje…
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Is there any undocumented flow for embedded FW development using a MicroBlaze inside the CL, with the AWS-FPGA HDK?
In my on-premise environment, using u200 card, and following the instructions fro…
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Why does the driver read the user BAR at address 0x2000 0x3000?!
It shouldn't even try to access the user BAR at all. It breaks the whole Xilinx/AMD AXI interconnect since these addresses aren't mapp…
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A few changes are needed for successful synthesis by the legacy Xilinx ISE toolchain:
- xst incorrectly implements the register file with ENABLE_REGS_DUALPORT = 1, but ENABLE_REGS_DUALPORT = 0 work…