-
A problem was found where code of a form similar to the below would leak data, presumably from stack:
```
let mut keys: Vec = Vec::new();
let r = 2;
let c = 0;
keys.push( (r, c) ).unwrap();
…
-
This is likely a known issue, but in any case: I was trying to recursively clone the current master branch (3ea245d304fca5d70a5e3ee700a3656970feb554) but it misses some repositories, which are either …
-
Hi, All:
after build a basic SoC configuration, there are two works has to be expands.
1. add our designed verilog based modules into current SoC configuration, and write linux drivers. what I k…
-
I came across your presentation for 36C3 and was wondering if you started working on TRNG and crypto cores:
![image](https://user-images.githubusercontent.com/3709037/71650373-b60ba100-2d15-11ea-8d8d…
-
Clock gating tasks:
- [x] add BUFGCE's for crypto domains
- [x] wire up crypto clocks to a pair of bits that wire-OR a "power on" signal from both the SHA control and the eventual Engine25519 cont…
-
I noticed a weird bug today where shifting the order of the `text` String in the `TextView` struct fixed a bug where it seems like some items after the `text` was being overwritten. It's hard to repr…
-
Calling `sleep_ms()` inside the main of shell.rs causes the interrupt handler inside another server to stop running for an interval equal to the sleep period. For example, I had to comment out this li…
-
Ran out of patience tracking this one down, but noting it as something to clean up later on.
This test case: https://github.com/betrusted-io/xous-core/blob/bee1f796ee3a64dc41c6af213bb45858f5f8a64c/…
-
Is it possible to load a binary onto an emulated LiteX / VexRiscv SoC in Verilator and debug it with GDB? If so, is there a tutorial on how to do this? I'm new to the LiteX ecosystem, and I see that `…
-
`gdbstub` makes it very easy to add a GDB server to any project. The current design uses long-polling to interact with the target. Conceptually, `gdbstub` sits between a network `Connection` and the `…