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```vhdl
type t1 is array (natural range) of std_logic_vector(7 downto 0);
type t2 is array (natural range) of std_logic_vector(3 downto 0);
function foo
generic (type t)
parameter (si…
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Expressions for conditions in VHDL flow control statements are only
supported for "=" and "!=". Relational operators such as "=" are
not supported. For the supported data expressions, they are compile…
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I suggest that you should rename it into something like vhdl-lsp or vhdl-rust-lsp.
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- [x] vhdl-tools by Cayetano Santos [https://gitlab.com/emacs-elisp/vhdl-tools](https://gitlab.com/emacs-elisp/vhdl-tools)
- [ ] vhdl-capf [https://github.com/sh-ow/vhdl-capf](https://github.com/sh-…
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This is a proposal: let us make ChiselVerify a more generic testing tool also for Verilog and VHDL designs. Something like, but better than, cocotb.
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I have build llvm and circt as mentioned in the README.md using submodule clone.
While installing moore using the command - `cargo install --path .` I get below build errors -
```
error[E0228]:…
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`physical.vhdl` does not contain all physical types that are commonly used for e.g. modelling analog circuits, like voltage, current, resistance etc.
Maybe we should even mirror the VHDL-AMS packages …
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Hi! I'm far from an expert in reading vhdl, but reading this:
https://github.com/MEGA65/mega65-core/blob/c533da5ee6e26d33a6dd5018aac888fd3ece1fcc/src/vhdl/cia6526.vhdl#L549-L554
it looks like th…
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Normally, when a function recognised as a test bench makes use of a function recognised as a top entity, these two end up in separate directories (and VHDL libraries). However, when `testBench` passes…
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There are quite a few Ethernet MAC cores, but mostly in Verilog. I've a project written in VHDL, use GHDL, and therefore looked for a core written in VHDL, and found this project.
The core was tested…
wfjm updated
3 months ago