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**Description**
Some yosys backends do not use separate user-constraint files (LPF) to map pins to ports. The "traditional" method of creating user constraints for these backends is to use an attribu…
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@eine I'm trying to add an ECP5 PLL to microwatt and looking at https://github.com/ghdl/ghdl-yosys-plugin/blob/master/examples/ecp5_versa/Makefile it seems I need components.vhdl from there to be able…
mikey updated
3 years ago
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Building ghdl-yosys-plugin as part of Yosys is not recommended and might become deprecated: https://github.com/ghdl/ghdl-yosys-plugin#build-as-part-of-yosys-not-recommended. Instead, it is suggested t…
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When Yosys is built without dynamic plugin loading support, using option `-m` produces the following error:
> ERROR: This version of yosys is built without plugin support.
However, some plugins/…
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Hello, I am trying to compile the plugin, but I got a compilation error, I have all dependencies installed, I paste the message error down the text. Thanks for this amazing project, I hope we can find…
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**Description**
Maybe a design has signals which are declared inside a `block` or `generate` declaration region. If these signals are initialized only and not further assigned, they result in an err…
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This is a "design note" inspired by #56 (especially https://github.com/stnolting/neorv32/pull/56#issuecomment-858008281 and https://github.com/stnolting/neorv32/pull/56#issuecomment-858149579).
Cur…
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**Description**
In https://github.com/ghdl/ghdl/commit/098e5e7fcb5863bec25214d1da4d946deb5d8453 was added support for Yosys "formal inputs". These are declared by attributes on signals, however they …
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**Description**
libghdl is generating unnecessary (for synthesis) midffs when code is split across multiple `if rising_edge(clock) then` blocks.
**Expected behaviour**
After https://github.com/LA…
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Together with @Paebbels, we've prototyped an 'extended-tests' repository for GHDL: https://github.com/umarcor/ghdl-extended-tests. The motivation is having quick feedback of relevant projects which we…