-
Hello
Problem:
I target a design for FPGA. I have know a couple of verilog module, build on a bottom-up approach.
I face strange behaviour when running the application : sound synthesizer . And I wa…
-
@nmoroze Thanks again for the Sphinx contribution. This is going to be great!
@WRansohoff
I really like the philosophy of auto generated html from source, but the default seems to be deprecated d…
-
Looking for a way to parse myhdl generated vcd dumps to extract the signals to pass to sigrok-cli for protocol analysis. (sigrok-cli doesn't support signal vectors)
-
Using /home/peter/miniconda3/envs/litex_fpga/lib/python3.6/site-packages/colorama-0.4.4-py3.6.egg
Finished processing dependencies for migen==0.9.2
[installing nmigen]...
Traceback (most recent cal…
-
So I hear a lot about a "cycle accurate C simulator" that is created for an architecture before the Verilog is written. This is apparently a home-grown C/C++ application that models the Verilog and ul…
-
Requirements:
- [ ] read, write, and read+write ports
- [ ] support for asymmetric width ports (eg. 4-bit write, 8-bit read)
- [ ] uninitialized, zero initialized, or initalized with arbitrary da…
-
Hello, I'v try the little sample of the convert function.
I used the example, the "width" be change by value "8" and replace it for all verilog "width"...
So, I want to generate the verilog RTL code…
-
In a first attempt to see how cocotb works I copied the adder example. Place the files adder.vhd, adder_model.py, test_adder.py and the makefile into one directory. Opened Windows Powershell in that d…
-
Is there any reason why kratos doesn't support verilog generate statement and genvar? This is very useful feature of verilog/systemverilog that makes code readable and easy to understand. Basically, I…
-
I'm working on a class project to apply _systems engineering_ concepts to a real life project. I would like to work on _GHDL_ because I did computer engineering for undergrad and I've done some experi…