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Hi, I'm trying to run simple ELF payload on Spike without PK desirably without any MMU.
I'm using rv32i ISA and built gnu-toolchain, pk and spike locally. All tests with PK works fine.
Now, minima…
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wsim --sim vcs rv32gc ~/cvw/tests/riscof/work/riscv-arch-test/rv32i_m/I/src/add-01.S/ref/ref.elf --lockstep
fails at the first instruction
The log shows ImperasDV is being intialized with the RV6…
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I buillt a toolchain for RV32IMC from riscv-gnu-toolchain project
./configure --prefix=/opt/riscv32 --with-arch=rv32imc --with-abi=ilp32
wrote a hello.c
#include
#include
int main(void)
{
…
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I'm using riscv-torture to test my RV32IC implementation. For this I create RV32I test cases and build them with `-march=RV32IC`. See https://github.com/cliffordwolf/picorv32/tree/master/scripts/tortu…
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Add a brief intro RISC-V to the wiki. Quick and dirty. Explain RV32I, LLVM. Link to datasheet.
The wiki autodeploys from the `mdbook` layout in `/book`.
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Hello,
I am trying to use this software to extract coverage. But failed. Does anybody can upload an example to try.
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# Background
Hey I've read the docs and it said that ports for other architectures are welcome but one should ask via mail.
I thought it would be better to ask this in an issue.
So I would like t…
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A few folks have requested support for the [ring](https://github.com/briansmith/ring) crate.
e.g. [here](https://twitter.com/0xVizualkei/status/1697329769904484752)
I didn't see an issue open for…
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I'm trying to pass a testlist to run a single test rather than the entire suite for faster iteration while I'm setting up the tests and debugging failures.
When I run `riscof run --config=config.in…
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Hi,
I tried to understand the concept behind pluggable pipeline but could not till now. Usually, instruction set architecture or the group of instructions for a architecture are defined by the set of…