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I.e., this graph:
I've tried www.veripool.org/verilog_sim_benchmarks.html (which is …
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While i was simulating the SweRV core on verilator. I found that it created few header files in the snapshot/default/ folder. One of the file is pd_define.vh. In that file I have encounter a line whic…
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It looks like the core has legitimate syntax errors where code refers to variables before they are declared. Example:
```
../../src/github/sv-tests/build/chipsalliance.org_cores_SweRV_EH1_1.8/src/ch…
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the EN2 RTL code already include AHB-lite ports, why doc metioned that it is not support ?
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Commit 12fca602172f6dfc3557575984cefa634353f6a4 have introduce changes in dhry related source files while dhry.hex and dhry_mt.hex was not updated (rebuild).
Now when using hex files from repo both …
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Hello,
I have successfully able to run this environment using verilator. However when I try to simulate this flow using 'xcelium', I get below error from makefile.
![Capture](https://user-images…
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```
$~/SweRV-ISS/build-Linux/whisper --interactive --newlib
whisper> poke m 0 0x295E94D3
whisper> s
#1 0 00000000 295e94d3 f 09 ffffffff7fc00000 fmax.s f9, f29, f5 +
#1 0 00000000 295e94d3 c …
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I'm adding support for SweRV EL2 in SweRVolf. It seems to run fine except for the debug interface. I can read and write RAM but after trying to access device memory through the debugger there's an err…
olofk updated
3 years ago
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