ogarnica TFG2020-21_RISC-V issues

ogarnica / TFG2020-21_RISC-V

Proyecto desarrollo chip RISC-V en tecnología STMicroelectronics

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Corregir memoria capítulo 1: Introducción (es) y (en)

#64 AndreaPCalvin closed 2 years ago
1
Correr síntesis con check_constraints

#63 AndreaPCalvin opened 2 years ago
0
Corregir memoria capítulo 1, 2, 3, 4, 5, 6, 7

#62 AndreaPCalvin closed 2 years ago
1
Añadir bumps

#61 AndreaPCalvin closed 2 years ago
0
Revisar warning síntesis de las celdas de librería que no tienen output pin

#60 AndreaPCalvin opened 2 years ago
2
Revisar reporte de swerv_wrapper_operating_cond_constraints.rpt

#59 AndreaPCalvin opened 2 years ago
3
Generar un nuevo netlist usando las librerías correctas y correr el PandR

#58 AndreaPCalvin closed 2 years ago
2
Comando no soportado: set_units

#57 AndreaPCalvin closed 2 years ago
1
Mandar indice del TFG

#56 ogarnica closed 2 years ago
1
Completar flujo PnR hasta el final

#55 ogarnica closed 2 years ago
3
Correr Conformal RTL vs post-PnR

#54 ogarnica opened 3 years ago
0
Elaborar script STA

#53 ogarnica closed 2 years ago
0
Flip-Chip con doble row

#52 ogarnica opened 3 years ago
0
Valorar si aumentar memoria DCCM en el script de configuracion a 2Kx39 palabras

#51 ogarnica opened 3 years ago
0
Confirmar que se están usando el archivo de constraints correcto en PandR

#50 AndreaPCalvin closed 2 years ago
3
Revisar error en mem_lib

#49 AndreaPCalvin closed 2 years ago
1
Modificar memoria TFG atendiendo comentarios Oscar

#48 ogarnica closed 2 years ago
0
Generar netlist con memorias STMicroelectronics

#47 ogarnica closed 3 years ago
1
Insertar memorias STMicroelectonics en RTL

#46 ogarnica closed 3 years ago
4
Incluir net fanout histogram (Innovus) en memoria

#45 ogarnica closed 2 years ago
0
Revisar capítulo de síntesis en Overleaf

#44 AndreaPCalvin closed 3 years ago
1
Trasladar comandos tiecells de `syn_swerv_nuevo.tcl` a `syn_swerv.tcl`

#43 ogarnica closed 3 years ago
1
Errores generación reportes en proc.tcl

#42 AndreaPCalvin opened 3 years ago
1
Scripts deben estar autocontenidos en el directorio de scripts

#41 ogarnica closed 3 years ago
0
Corregir error clock_gating cell in `pd_defines.v`

#40 ogarnica closed 3 years ago
0
Reorganizar directorios

#39 ogarnica closed 3 years ago
1
Scripts **DEBEN** usar configuración `default_pd`

#38 ogarnica closed 3 years ago
1
Limpiar directorio scripts de síntesis

#37 ogarnica closed 3 years ago
0
Revisar presencia valores constantes (1 y 0) en netlist post-synthesis

#36 ogarnica closed 3 years ago
0
Insertar IO pads post-synthesis

#35 ogarnica closed 3 years ago
1
Floorplan IO

#34 ogarnica opened 3 years ago
1
Insert scan chain during synthesis

#33 ogarnica opened 3 years ago
0
Leer tutorial Innovus

#32 ogarnica closed 3 years ago
0
PnR standard cells

#31 ogarnica closed 3 years ago
1
Leer documento flow Cadence

#30 ogarnica closed 3 years ago
0
Leer documento IO

#29 ogarnica closed 3 years ago
0
Ver video PnR

#28 ogarnica closed 3 years ago
0
ERROR: Cannot find corner default_rc_corner in layerResPerDBUForCorner table

#27 ogarnica closed 2 years ago
1
Revisar celdas con warnings PandR

#26 ogarnica opened 3 years ago
3
Regenerar configuracion procesador

#25 ogarnica closed 3 years ago
2
Warnings in read_rtl_swerv.tcl

#21 ogarnica closed 3 years ago
1
¿Cómo hacer que el read_rtl lo tire a ${logFile}.log?

#20 ogarnica closed 3 years ago
2
Set Operating conditions

#19 ogarnica closed 3 years ago
0
Completar sustitucion módulos clock gating

#18 ogarnica closed 3 years ago
0
Buscar tutorial o user guide de Genus

#17 ogarnica closed 3 years ago
2
Genus se detiene cargando tool scripts

#16 ogarnica closed 3 years ago
1
Determinar porque no corren las licencias

#15 ogarnica closed 3 years ago
1
Crear estructura de directorios en repositorio

#14 ogarnica closed 3 years ago
1
Configurar SweRV corriendo scripts de configuracion

#13 ogarnica closed 3 years ago
1
Leer archivos verilog desde Genus

#12 ogarnica closed 3 years ago
2