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**LEC Formality Error code errors reported in csrng_reg_top.sv**
Warning: You are using the unique case but some items may overlap. (Signal: addr_hit[0] Block: /csrng_reg_top File: RTL/csrng_reg_to…
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Hi, trying to track down an issue, I believe it's in the plugin but it could also be in surelog.
I am using the default submodules except for https://github.com/chipsalliance/yosys-f4pga-plugins/pu…
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Verilator released the new version 5.021 last January 17, 2024. It supports some Verilog-AMS function, for example "wreal". I wanted to investigate the specification if we can we use it for analog mod…
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i tried to change a python simulation in to a icarus-cosimulation. it seems to only work if i remove the **tb.config_sim(trace=True)** statement.
otherwise it says: _AttributeError: 'Cosimulation' ob…
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Hi all,
I have a problem with the axi_xbar: I use a configuration with 4 masters and 2 slaves. The second master writes valid data to the interconnect and the data is confirmed by the slave, but by…
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https://verificationacademy.com/forums/systemverilog/function-arguments-not-initializing-variable-inside-body#reply-54684
Inside a static function, variable declaration with initialization requires…
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By sticky, I mean the behaviour described in the standard (I only have 2001, section 27.32 describes the function):
`When vpi_put_value() is called for an object of type vpiNet or vpiNetBit, and wi…
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I have seen that a post about ChiselSim has been recently published. It says that ChiselTest is not longer supported for new chisel features.
So, what are the future developments for chiseltest?
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### Description
Between the 16. and the 19. of October something caused the entropy source coverage to plummet to around 30 to 40%.
To verify this I ran the following command with a 0.1 reseed-mul…
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Hi,
With regard to:
https://github.com/svunit/svunit/blob/5b785137a7563ac0b145fa660c2529bb33037d9d/svunit_base/svunit_internal_defines.svh#L22-L27
I get the following output.
```
$ runSV…