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When we use the JTAG programmer to download the fpga.bit file to the Alveo u50, the server will automatically restart. After restarting, the lspci will not be able to locate the board, and the blue li…
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Hi all, our lab has only a soc xilinx zcu102 and i'm a freshman of FPGA developing. I want to verify zynqnet on zcu102 so i have to transplant it from 7045 to zcu102. Are there any docs or other proje…
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Dear mr. @dgschwend,
I'm interested to test your CNN on Xilinx UltraScale+. I've generated the fpga_top IP with Vivado HLS and used it to create an hardware platform for the ZCU102 part with Vivado.…
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Hello @ikwzm,
I have been following your instructions for installing XRT on Debian 10 (ARM64) as described in the repository. Previously, I posted an issue, and thanks to the feedback, I now have a…
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Hello, could somebody give a short explain about the differences between the file VC707Shell.scala and VC707NewShell.scala under path fpga-shells/src/main/scala/shell/xilinx/? Do they complement each …
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In a new end to end example, we try to evaluate tfhe-rs-bool code on an FPGA. To communicate with an Xilinx Alveo FPGA we use the XRT library.
There is a problem during the initialisation of the FP…
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Dear all,
what would be needed to add support for Xilinx Virtex 6 series of FPGAs?
I guess the reason that there is no support so far is mainly due to the fact that there was no demand. Or are t…
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Install jenkins and compile FPGA
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Currently triSYCL does not build with MSVC 2017, mostly due to unsupported __attribute__ statements used.
An exerpt:
```
git grep -i noinline
include/triSYCL/detail/instantiate_kernel.hpp: …
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I have a kubernetes cluster running with two nodes, using Calico CNI. One node has two U55C's and the other has 1 U55c installed, all cards flashed and XRT installed on all nodes. I am following the i…