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I am wondering whether it will be possible to adopt Zynq MPSoC flow to implement Vitis AI on Xilinx RF SoC platforms like ZCU111 or ZCU1275. These devices also have the same ARM A53 QuadCore PS.
If i…
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We need to bring the standby power down for the Parallella to make sure people don't burn up the board just by turning it on. Can we try turning on the following features in parallella_defconfig and c…
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# Bug Report
## One-Line Summary
Unexpected behavior for clock configuration.
## Issue Details
### Steps to Reproduce
* First confirm that some clock options do work.
* ``` $ a…
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in
```
root@analog:~# cat /etc/rpi-issue
Raspberry Pi reference 2019-08-02
Generated using pi-gen, https://github.com/RPi-Distro/pi-gen, 29d362e5443c4f591885a4de3cbd48d4239efb70, stage6
root@a…
rgetz updated
3 years ago
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/home/uisrc/linux/zynq/install/libev/lib/libev.so.4.0.0: error adding symbols: File in wrong format
collect2: error: ld returned 1 exit status
src/CMakeFiles/rtty.dir/build.make:244: recipe for targ…
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This is an inquiry to the wider audience who are working on getting NVDLA running on a FPGA platform--we'd like to share what we are doing and check progress on other groups out there .
we are putt…
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Hello,
I am a master's student working on my Master's Thesis, and I am experiencing several issues while trying to compile the XRT library on a Debian 10 environment on a Zynq Ultraescale + XU8 Mer…
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At global scope:
cc1plus: warning: unrecognized command line option ‘-Wno-parentheses-equality’
VTestHarness.mk:69: recipe for target 'SimDTM.o' failed
make[1]: *** [SimDTM.o] Error 1
make[1]: Lea…
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- Situation:
- adds uartps to hw design (but uartps is not a debug channel for the developer)
- select another uart(ns16550) for STDIN and STDOUT in BSP(for fsbl) setting.
- uartps should not…
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Hi,
I wonder if there is a feature of controlling the voltage sampling range of the QICK ADC for optimal dynamic range?
In the Zynq page, there is a the option of integrated digital step attenua…