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I ran into something that seems like a bug, so I wanted to let you know and ask what you think. When I parse one of my ECEN 220 projects into spydrnet, one of the wire connections isn't right.
The …
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The Resistor generator function may throw:
```
throw new ReadingException("Invalid parameter for resistor: " + parameter.Image);
```
This should include the ```parameters``` (netlist.Text) line # …
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- the if-block in l. 67:
`if (std::all_of(net_temp.begin(), net_temp.end(), ::isdigit)) {...}`
can't be entered, since the `get_net_name` function already adds the "NET_" prefix to a net with only …
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I am trying to run FAULT on Swerve el-2 design. I have DC synthesized netlist which is mapped on Sky 130 A library. When I try to run the cut command following error appears.
Command:
`
fault cu…
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@acomodi
I was trying to modify the symbiflow counter test to take an input from one of the switches, and ran into an interesting error where the input pin for a switch was not being routed correctl…
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There are several tests that need to be added that relate to parsing and composing and other important portions of our code.
I think we can start to make our testing framework much more robust by a…
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Hi,
I just updated to Alchitry Lab 1.1.2 and it fails to build on Alchitry Cu using IO Element Demo base project. I am using Windows 10. It gives the following error:
`Error : can not print out lo…
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Hi,
I have following circuit:
```c#
namespace Test
{
class Program
{
public static void Main(string[] args)
{
Example.Run();
}
}
pu…
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Hi,
is it possible to get more advanced example on how to use SpiceSharpBehavioral with circuit like this one?
```
I_M 0 N1 0.025
X_entry1 N1 0 N2 entry_1
X_entry2 N1 0 N3 entry_2
.subckt …
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## Steps to reproduce the issue
Start Yosys and do this:
```
read_verilog CpuComplex.v
read_verilog -lib -D_ABC +/ice40/cells_sim.v
hierarchy -check -top CpuComplex
proc
write_json CpuComp…