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This will allow us to bring in the PicoRV32 with ENABLE_DIV=0, and use the freed resources in the FPGA for other things.
This will require clang-15. Is this sensible to do until Ubuntu 22.04 LTS ge…
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In https://github.com/efabless/caravel_mgmt_soc_litex/blob/c741d6145024e621dc10b7f511a306e4858a92f9/litex/caravel.py#L186 the defined mprj size is much smaller than the original management soc mprj me…
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@bjoto wrote:
> The picorv32 on the key is built with ENABLE_DIV=0, and we're compiling the source (fw/app) with the "m extension" enabled. The m-ext includes div/rem so we're just lucky that we're…
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[17:03:11:297] \ | /
[17:03:11:297] - RT - Thread Operating System
[17:03:11:303] / | \ 3.1.3 build Sep 7 2022
[17:03:11:309] 2006 - 2019 Copyright by rt-thread team
[17:03:11:309] Hel…
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RISC-V ISAs provide a set of up to 32×64-bit performance counters and timers.
RV32I provides a number of 64-bit read-only user-level counters, which are mapped into the 12-bit CSR address space and…
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### Description
When I passed the parameters about verilog_files in config.tcl, I found that the absolute path, or the same way of passing parameters as in json caused the file to not be found, I w…
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starting from picorv32, we want to use asynch reset and maybe convert it to systemverilog
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To generate the RISCV firmwares for BARVINN simulation, I am trying to compile the convolution C code in `csrc/conv/` . So I installed the rv32 RISCV compilation toolchain as per the Picorv32 [instruc…
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To reproduce:
```
cd examples/picorv32_primes
mcy init
mcy run
```
1. sby is now requiring a `[tasks]` section with regex (https://github.com/YosysHQ/sby/issues/76), but this wasn't added to `…