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### Hi. im following the steps in FINN/FINN/backend/fpga/README.md. Im doing the build of SDx executing this steps:
1) " ./make-sw.sh lfc-max bnn hlsweights" choosing HLS (h) [OK]
2) "./example/…
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I was checking out the mentioned example and I noticed this:
https://github.com/Xilinx/SDAccel_Examples/blob/1e273f6ef01073f878a4c2b5ca4d6ad5aec7e616/getting_started/kernel_opt/systolic_array_ocl/s…
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I spent several weeks to run YOLO / ML Suite on AWS F1 and finally I can see the results. I did not try any change on the design and I just wanted to run and see the result. The reason why it made me …
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I am trying to compile the attached code (simple N-body) with the current versions of the compiler (up-to-date `sycl/unified/master`) and SDAccel (2018.3) and a self-compiled XRT (up-to-date `2018.3`)…
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https://community.reconfigure.io/t/simulation-problem/433
When running `reco sim run` reco should follow the resulting logs until the job has ended and there will be no more logs. This is not the c…
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Hi,
I am integrating our IP into SDAccel Environment. What I have done are inside IPI GUI. I have checked "Use Auxiliary (non-AXI) Signal Ports" in "Enable IP Interface" tab inside VIVADO. Also I con…
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Environment: Ubuntu 18.04 + ROCm 2.2 + TVM (built from current master with ROCM = ON)
I ensure the target TVM library successfully detect and link with ROCM, and the tuning procedure runs successfu…
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Any issues related to HDK or SDK should be filed on FPGA development Forum.
The [AWS FPGA Development User Forum](https://forums.aws.amazon.com/forum.jspa?forumID=243) is the first place to go to p…
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Hi There
Today I tried building TVM from source to upgrade my existing tvm install and it failed for some reason. `cmake ..` output is below followed by the output of build.
```
root@3fc527cf9528…
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Can we use the "create_sdaccel_afi.sh" which is provided by AWS to generate the AWS FPGA Binary file? I found that when I used this script to generate awsxclbin file, the output split file would run …