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Hello sir, I am a newbie in PCIE, I recently want to use cocotbext-pcie to verify the RC->xdma->AXI-MM BRAM datapath, I refer to the testcase in the verilog-pcie, but I only found the connection betwe…
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Unit test feature has many consideration points from simulation only description like delay and clocking to testing framework like UVM.
I'll add minimal support of unit test because these considerati…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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I face a big problem while running the task get_stocks_summary.py
I can get the original_df
Here're data
```
{'AOS': {'regularMarketOpen': '70.91', 'previousClose': '70.65', 'dayHigh': '71.…
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In the `v1.0` firmware, the `amdc_encoder_v1.0` IP core interfaces to the "ABZ" encoder hardware. Read about encoders [here](https://docs.amdc.dev/hardware/subsystems/encoder.html). It keeps track of …
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@riscv-steel I'm a bit confused by how the testing framework is meant to be compiled. It points to a testing framework repo, but doesn't give clear instructions how to reproduce. Could there be step-b…
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### Description
Hello,
we're trying to simulate aes_core module using ModelSim simulator with Vivado IDE and we're getting this error:
# ** Error: ../../../../hw/ip/prim/rtl/prim_lfsr.sv(467): (v…
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**Describe the bug**
i can use vivado or iverilog run my .v code and tb, but can't run on this extension ,i am new in vscode and verilog……
**To Reproduce**
2022-08-12 13:33:24: /home/mrpp/anacond…
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```haskell
module VIOtest where
import Clash.Prelude
import Clash.Cores.Xilinx.VIO
import Clash.Annotations.TH
type Dom = XilinxSystem
viotest ::
"clk" ::: Clock Dom ->
"inp" ::: Sig…