Severson-Group AMDC-Firmware issues

Severson-Group / AMDC-Firmware

Embedded system code (C and Verilog) which runs the AMDC Hardware

http://docs.amdc.dev/firmware

BSD 3-Clause "New" or "Revised" License

30 stars 5 forks source link

issues

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Validate that the `v1.3` codebase still correctly logs data for non-integer sampling rates

#404 npetersen2 opened 6 days ago
0
Enabling/disabling sensors during operation leads to inconsistent scheduler tick loop time

#402 codecubepi opened 1 week ago
0
Fixes for new Timing Manager mode

#401 codecubepi closed 5 days ago
3
Updates to Inverter/PWM IP

#400 codecubepi closed 2 weeks ago
2
Problem with new Timing Manager sensor mode

#399 codecubepi closed 1 week ago
20
Inverter IP Duty Ratio Latch Update

#398 codecubepi closed 2 weeks ago
2
Manual Merge of #392 into Staging Branch

#397 codecubepi closed 4 weeks ago
4
AMDS Driver: Make timeout values configurable

#396 codecubepi opened 1 month ago
0
Profile math operations running in C code

#395 npetersen2 opened 1 month ago
0
Final fixes to new AMDS Driver: Invalid Data and Timeout

#394 codecubepi closed 1 month ago
2
New AMDS Interface not timing out correctly

#393 codecubepi opened 1 month ago
3
Change scheduler functionality to align with timing manager

#392 annikaolson closed 1 month ago
2
Update/remove scheduler task-rate defines based on new timing manager integration

#391 npetersen2 closed 4 weeks ago
2
Update README

#390 npetersen2 closed 1 month ago
0
Random invalid data in new AMDS driver?

#389 codecubepi closed 1 month ago
3
Testing of new AMDS Interface

#388 codecubepi closed 1 week ago
2
Add way to read FPGA registers at runtime

#387 codecubepi opened 1 month ago
0
Replace all hard-coded FPGA addresses with the defines given by xparameters.h

#386 codecubepi opened 1 month ago
0
Re-order slv_regs in Timing Manager IP

#385 codecubepi closed 1 month ago
4
Merge new AMDS driver and other FPGA changes back into v1.3-staging

#384 codecubepi closed 1 month ago
2
Manual Triggering in Timing Manager

#383 codecubepi closed 1 week ago
2
Invert PWM Signals during Switching Operation

#382 codecubepi closed 1 month ago
2
Add trigger qualifying on all_done in timing_manager?

#381 codecubepi closed 1 week ago
6
Remove PWM Carrier High/Low Trigger logic from Eddy Current Sensor IP

#380 codecubepi closed 1 week ago
2
Fix Timing Management Logic in FPGA

#379 annikaolson closed 1 month ago
2
Update docs with info about new timing manager system

#378 npetersen2 closed 1 month ago
2
Modify scheduler to be configurable between ISR sources per new timing manager

#377 npetersen2 closed 4 weeks ago
9
Fix timing acquisition logic

#376 annikaolson closed 2 months ago
1
WIP: Release v2.0.0

#375 npetersen2 opened 2 months ago
0
Add REV F support to v1.3 release branch

#374 npetersen2 closed 1 month ago
3
Fix timing manager to report correct sensor sampling time

#373 npetersen2 closed 1 month ago
2
WIP: Release v1.3.0

#372 npetersen2 opened 2 months ago
2
Add changelog notes for v1.2.0 release

#371 npetersen2 closed 2 months ago
0
Debug ADC issue with timing manager

#370 annikaolson closed 2 months ago
1
pcbtest application does not work on REV E/F hardware

#369 npetersen2 closed 2 months ago
1
Fix pcbtest application for REV E/F hardware target

#368 npetersen2 closed 2 months ago
3
Add firmware support for AMDC REV F

#367 codecubepi closed 3 months ago
1
Add firmware support for new AMDC REV F hardware

#366 npetersen2 closed 3 months ago
2
Add support in timing manager for AMDS sensor

#365 npetersen2 closed 1 week ago
3
Debug PL-PS interrupts

#364 annikaolson closed 3 months ago
1
Make/Find Basic Zynq-7000 Interrupt Project

#363 codecubepi closed 3 months ago
3
Update encoder interface in FPGA

#362 annikaolson opened 4 months ago
0
Update REV D & E Block Designs for v1.3

#361 annikaolson opened 4 months ago
1
Merge FreeRTOS base code with FPGA I/O timing management code

#360 npetersen2 opened 4 months ago
1
Merge initial FreeRTOS Code into v2

#359 codecubepi closed 2 months ago
3
Added I/O timing management in FPGA

#358 annikaolson closed 2 months ago
1
Verify that the cumulative timing statistics for each sensor is being computed correctly

#357 annikaolson closed 2 months ago
12
Verify timing results are accurate on hardware

#356 annikaolson closed 6 months ago
0
Test that when you enable each sensor, we can probe with the scope to see the physical sensor is actually being driven

#355 annikaolson closed 6 months ago
3
Test new I/O timing management on hardware

#354 npetersen2 closed 2 months ago
0