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hello sir
i am not familiar with mojo but instead i have spartan 6 xlx9 .
which software did you use for compile your code .
and if it is possible for you i want to contact with you and ask some q…
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Why are two general-purpose register groups designed in darkriscv.v,
Not like one of the riscv specifications,
Is it to support multi-core?
reg [31:0] REG1 [0:31]; // general-purpose 32x3…
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As the HDL-generation part has had a big overhaul, it would be great if also the Xilinx-FPGA path can be tested.
As I mainly use Intel (Altera) FPGA's, I do not have the ability for the moment to che…
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Hey guys,
it seems the negative range (-50...-0) is not interpreted so that the glitch is moved to the second half of the clock period as mentioned in the API docs. Instead the glitch is starting a…
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**Description**
Latches are usually not what you want in your design, but sometimes they are necessary afterall. Currently, ghdl crashes when trying to synthesize one.
**Expected behaviour**
GHDL…
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dcm_24MHZ ,dcm_25MHZ and dcm_64 MHz are missing in source files
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Hi. This problem appears with an example from ISE, where a UNISIM component is used. To simplify the example I provided the primitive definition in the same file.
```
library ieee;
use ieee.std_log…
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I was [comparing Yosys against ISE and Vivado](https://github.com/rodrigomelo9/yosys-versus), using examples provided by Xilinx. I found only this problem related to a Single-port memory inference whe…
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Hi
I finally tested your XC7A35T code and it’s working good. Good job ! We could port the PCI and Ethernet code and I could help you.
I’m actually trying to port the hostmot2 SPI firmware to SLX16-…
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PIO Core Call Error: "The current working directory /home/anderson20/Documents/PlatformIO/Projects/Wifi will be used for the project.\n\nThe next files/directories have been created in /home/anderson2…