-
- Situation:
- adds uartps to hw design (but uartps is not a debug channel for the developer)
- select another uart(ns16550) for STDIN and STDOUT in BSP(for fsbl) setting.
- uartps should not…
-
**Environment:**
OS: Windows
SW Version: Version: v1.0.0-rc3
Writing and configure a Kuiper Image in the same step, won’t copy BOOT.BIN and system.dtb in /BOOT after the writing process is comple…
-
Hi, do you mean that this project works fine on the fpga?
And I would appreciate it you could give some tutorial about how to build and install on an fpga?
-
This caused me several lost hours, but ultimately the fix is easy, just specify the type. I am working with a Vivado generated .bit file for the Zynq processor, I am also using the XVC cable via "xv…
-
A suggestion to provide API on mynteye to allow single camera raw output + synchronoized IMU data for mono+inertial users.
With one camera, (hopefully) the required b/w is only half, then a promis…
-
@Mluckydwyer I have run the demo on this https://github.com/Xilinx/systemctlm-cosim-demo/blob/master/docs/zynq-7000-getting-started-guide.md and was getting some value in shell using the devmem 0x400…
-
if I intergrated nvdla into FPGA successfully , can I just run "nvdla_runtime" to start inference with the FPGA conncted to hostPC ? is this feasible?
Or, is nvdla_sw only designed for simulation ??…
-
I try to get ethernet with u-boot (goal is to tftp).
It seems to crash when auto negociate the link. Any advice ?
I join defconfig and dts i modified for u-boot, inspired by the linux ones. I have …
-
I received my board a few days ago and now I am in the process of testing it but after connecting it to my computer this is the only I get:
```
1.0.0.47 (Dec 07 2017 - 00:36:15 +0800)
Model: Zy…
-
Old OmniVision sensors (including the OV7670) use the SCCB interface instead of I2C. It's basically the same, but the ACK bit is don't-care, and the SCL line is not open collector (always driven by th…