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I'm trying to run the bare-metal program on Arty-a7-100t, but I run into an error when trying to download the program on the board:
xsdb% dow -clear boot.elf …
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Hello, we are trying to implement pulpino on Arty a7 35t but it is showing the following error. Can anyone please help us with this?
``````
source pulpino.tcl -notrace
CRITICAL WARNING: [Board 49…
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I was told on IRC that setting VPR_SEED may be a workaround.
I've repeated the command, after deleting the build folder each time:
`TARGET="arty_100" make | tee `
1) `export VPR_SEED="--seed 134122…
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The [Getting Started Guide](https://sifive.cdn.prismic.io/sifive%2Fed96de35-065f-474c-a432-9f6a364af9c8_sifive-e310-arty-gettingstarted-v1.0.6.pdf) does not state that this project won't build for Art…
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Hello,
We are trying to run an model in CFU playground. We followed the steps we can able to run pdti8 model in ArtyA7 board but what we want to do is to send our custom model which we trained and co…
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![image](https://github.com/litex-hub/linux-on-litex-vexriscv/assets/170522054/4bfc60c1-9c52-4d4c-bff9-abb332f085c2)
i connected the board and I got this issue after running ./make.py --board=arty --…
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Command: ./make.py --board=arty_a7 --cpu-count=1 --toolchain=symbiflow --build
* I did remove the extra xadc for the arty in the make.py line 92
Error:
```
Executing module `synthesize`:
[1…
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The Digilent Arty A7 board is an reasonable cheap, fairly large, modern and extremely common FPGA development board.
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Hi,
I have been trying to do the SoC example for the Arty A7 and I had a problem when it is the time to add the .bram_tcm file. My doubt is how it is possible to attach the software file in the sy…
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VTR fails with the following message when running the code below:
```
Error 1:
Type: Blif file
File: top.eblif
Line: 204
Message: Failed to find matching architecture model for 'ISERDESE2'
`…