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Hello,
I'm converting .lib files to .db with lc_shell. Everything got converted except for _SEQ_ modules for both timing models (NLDM and CCS). An example of error in the following:
```
lc_shel…
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Functional APIs more directly represent quantum computing circuit diagrams / graphs.
Really, we can support a directed asynchronous graph (similar to neural network programming) so we should change…
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Hi,
As mentioned in the discussions, I am interested in a "batch" feature that would allow vuegraf to be run asynchronously without losing data or requiring user logic with --history to catch up. T…
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| Clock | Reset | Enable | Initial | Name |
|-------|-------|--------|---------|------------|
| X | | | | `dflipflop` |
| X | | | X | `dfl…
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nRF24L01 2.4GHz Radio/Wireless Transceivers How-To
http://arduino-info.wikispaces.com/Nrf24L01-2.4GHz-HowTo
data sheet
http://yourduino.com/sunshop2/index.php?l=product_detail&p=188
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time python2 slow.py
real 0m6.487s
user 0m0.360s
sys 0m0.030s
```
from circuits import *
class a(Event): pass
class b(Event): pass
class Slow(BaseComponent):
@handler('started')
d…
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Can we have a slower clock than 1 hertz? When I set it to `0.5` I get an integer underflow to a beyond fast clock but to me very slow clocks are perfectly valid. My circuit only appears to work while …
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**Issue by [mtrberzi](https://github.com/mtrberzi)**
_Thursday Jul 03, 2014 at 16:37 GMT_
_Originally opened as https://github.com/manifold-lang/manifold/issues/117_
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One point of contention wil…
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This is a continuation of #1977
I was pleasantly surprised that after trying snapshot releases of Mumble, it does not freeze rest of Windows anymore during startup, however during that time Mumble…
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Implement all Primitive Operations in Firrtl [spec](https://github.com/freechipsproject/firrtl/blob/master/spec/spec.pdf)
Then we can parse firrtl, dynamically build the circuit by components, then w…