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The Bluespec compiler emits Verilog which makes **[Yosys](https://github.com/yosyshq/yosys)** somewhat unhappy:
```
1.3. Executing Verilog-2005 frontend: /tmp/yosys-bsv-v-QxaOnJ/keccak.v
Parsing …
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### Issue
When using the build option STP_STUB=1 during building in order to disable STP, BSC fails to build with error
```
/build/bluespec-git/src/bsc/inst/bin/bsc -stdlib-names -bdir /build/blues…
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```
export BLUESPECDIR=/tmp/bsc/inst
/tmp/bsc/util/bluetcl-scripts/expandPorts.tcl foo mkfoo mkfoo.v
couldn't read file "/tmp/bsc/inst/lib/tcllib/bluespec/portUtil.tcl": no such file or directory
…
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Flute currently bans the compressed hint encodings: at least C.NOP with nzimm != 0 and c.ADDI with nzimm == 0. I'm not sure if this is based on a past version of the spec that reserved these, but the …
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This issue is where we track the necessary skills required to write and design hardware.
# Bluespec SystemVerilog
- [ ] [Lecture 1](https://www.youtube.com/watch?v=IdTSgYv8PUM)
- [x] Pragnesh…
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This can be implemented by using a sliding window and a second BAR. The Xilinx Core does not support this feature directly, though. Will use a little Bluespec Module that has one configuration registe…
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Hi, I am trying to run Linux in simulation. I followed the instructions in the linux.gen file but I get the following output.
INUX_SOC=yes EMULATOR=../../../main/c/emulator/build/emulator.bin VMLINUX…
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I get the error below every time I try to use `cover property`.
Error message:
```
Internal Bluespec Compiler Error:
Please report this failure to the BSC developers, by opening a ticket
in t…
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## Steps to reproduce the issue
```
$ yosys -V
Yosys 0.9+4052 (git sha1 687f381b69, gcc 10.3.0 -fPIC -Os)
$ cat top.v
`default_nettype none
module Parametrized(input wire clk, output wire le…
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I build MAERI with the latest bluespec compiler in the repository https://github.com/B-Lang-org/bsc and gcc in version 7.5.0, I use the default configs to run the simulation ( i.e. run `MAERI -r`).
…