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> Note: I'm not sure if this should be an issue or a discussion. I think you can convert between them. Feel free!
I'd like to make two small suggestions to the rule syntax. I realize this is a topi…
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Hi,
I've been trying to use `sqrtFP` from the `FloatingPoint` library, and I was getting incorrect results. I then ran `make check` in `testsuite/bsc.lib/FloatingPoint` (with `testArith = True`) an…
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Currently, at synthesis boundaries all interface fields get turned into ports whose types are simply flattened bit vectors. This is rather annoying when trying to instantiate a Bluespec-synthesized m…
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Given this BSV code:
```bsv
package Foo;
import Vector::*;
module helloWorld#(Vector#(2, Reg#(UInt#(32))) v, Reg#(Bit#(64)) idx)(Empty);
rule hello_world;
v[idx]
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There is support for `$test$plusargs : String -> ActionValue Bool` in Bluesim, which just returns whether an argument was provided on the command line with `+`, i.e. `sim.exe +foo` means `$test$plusar…
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This is with a custom `maxOtherSize` (I set it to 10% instead of 5%). Maybe this is the cause?
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类似于这种检索方式，图片来自Verilog-HDL/SystemVerilog/Bluespec SystemVerilog插件的例化方式。
当前例化方式直接列出来所有v文件的方式，…
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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R language isn't included in markdown-gfm-recognized-languages
## Expected Behavior
The list in `markdown-gfm-recognized-languages` includes the item "R"
## Actual Behavior
It does not exi…
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A couple of questions first
- Your IDE/editor (e.g. vscode, emacs,...) you use with verible LSP ?
- VS Code
- IDE version:
- 1.82.2
- What other SystemVerilog plugins are active alongs…