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# Experience of running hybrid CHERI userspace on seL4 | Sid Agrawal
In this article, I share the experience of getting to a point where we could run userspace applications in seL4, which had CHERI c…
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Basically we should remove `pc_alignment_mask()`:
```
function pc_alignment_mask() -> xlenbits =
~(zero_extend(if misa[C] == 0b1 then 0b00 else 0b10))
```
The logic here is kind of hard to …
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Currently MiniRust defines how pointers are encoded and decoded pretty precisely. This might be too restrictive for CHERI so we might have to figure out a way to leave this more abstract.
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The draft HTML version of the RISC-V ISA manual is available for download on the release pages but is not currently hosted on a webpage. Could it be published on RISC-V's GitHub Pages, similar to how …
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The AArch64 backend implements a number of different strategies for MachineOutliner which are used to reduce overhead / improve code size savings:
* Default - the outlined code uses a normal call s…
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## Observed Behavior
We see a case that an illegal CHERI LOAD instruction is issued in the pipe, it does not get squashed and is sent for execution to the memory from where it picks up a data v…
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## Observed Behavior
In the case of multiple bit manipulation instructions, such as BINVI, the result of the operation is computed incorrectly due to an incorrect operand. The operand value passe…
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A bit in `Xenvcfg` has recently been allocated in the CHERI spec to enable/disable CHERI at different privilege levels. Looking at https://github.com/CTSRD-CHERI/cheri-specification/issues/69 I think …
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This a placeholder to note that the pointer masking extensions (which are mandatory in RVA23) `Smmjpm`, `Smnjpm` and `Ssnjpm`, need to be analysed in the presence of CHERI.
https://github.com/risc…
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Other RISC-V extensions which add state to the machine (F and V) each have two bits allocated in `mstatus/sstatus` for lazy context save/restore, and also to restrict access to the new state.
To be…