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```
muralivi@muralivi-macbookpro:~/cheriot/cheriot-rtos/examples/error$ cat hello.i
void __attribute__((cheri_compartment(("hello")))) say_hello()
{
xoo::bar();
}
muralivi@muralivi-macbookpro…
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## Observed Behavior
We see a case that an illegal CHERI LOAD instruction is issued in the pipe, it does not get squashed and is sent for execution to the memory from where it picks up a data v…
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Currently MiniRust defines how pointers are encoded and decoded pretty precisely. This might be too restrictive for CHERI so we might have to figure out a way to leave this more abstract.
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While reviewing static analysis reports on some CheriBSD ports, I came across this [code](https://github.com/CTSRD-CHERI/chericat/blob/a69d6b8af9c325a861fe5d438f3b7eb34dfaa187/src/mem_scan.c#L289C1-L3…
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The draft HTML version of the RISC-V ISA manual is available for download on the release pages but is not currently hosted on a webpage. Could it be published on RISC-V's GitHub Pages, similar to how …
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## Observed Behavior
In the case of multiple bit manipulation instructions, such as BINVI, the result of the operation is computed incorrectly due to an incorrect operand. The operand value passe…
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(On second thought, moving this out from #340)
There's a subtle assumption in most CHERI work to date that the address field of a capability is a full machine word and is one half of the CHERI capa…
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In section 5.7 Disabling CHERI Registers the description points to Sections 3.3 and 8.5 for instructions that should generate exceptions. Whilst the text does say CHERI instructions, it is quite easy …
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https://github.com/rems-project/cerberus/commit/20d9d5ce2e982c4744ef6911a25a3be9307518f3 fixed the existing CN lemma tests, but these should really be part of the CI. This requires re-working the CI s…
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A bit in `Xenvcfg` has recently been allocated in the CHERI spec to enable/disable CHERI at different privilege levels. Looking at https://github.com/CTSRD-CHERI/cheri-specification/issues/69 I think …