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**Describe the bug**
When I click to the Schematic viewer button, the out put is :
2024-03-11 12:53:09.710 [error] Yosys failed.
2024-03-11 12:53:09.716 [info] yowasp-yosys -p "read_verilog -sv …
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Dear,
is there already support for VHDL design entry via GHDL Yosys plugin ?
Hoping to receive a positive reaction, I remain,
Greetings,
Patrick Pelgrims
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I am trying to use eqy in conjuction with [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin). However, I get the following error:
```
ERROR: conflicting matches for gold bit $auto$ghdl.c…
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Using `yosys` and `synlig` compiled from sources, I'm trying to convert SV into V (without synthesis), as follows:
```
yosys -Q -p "
plugin -i systemverilog
read_systemverilog counter.sv
hierarch…
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I've tried to extend the apio SConstruct to also support a VHDL toolchain, making use of yosys and the ghdl-yosys-plugin for synthesis. For simulation, plain ghdl is used instead.
The code is [here…
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### Version
Yosys 0.36+85 (git sha1 f26495e54, clang 10.0.0-4ubuntu1 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
[yosys_crash.zip](https://github.com/YosysH…
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**Describe the bug**
When trying to generate schematic of my designs in VHDL, which are synthesised successfully using GHDL, it failed when trying to generate schematic with the Yosys command generat…
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Is there a plan to integrate ghdl yosys plugin to yosys for windows platforms ?
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Both Yosys and GHDL work fine, but when compiling the VHDL code I always get the same error:
```
dyld[69836]: missing symbol called
```
I have tried using it along with the oss-cad-suite envi…
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When trying to assign a pin to HiZ I get a hard low drive instead. Reproducer below. I dub this bug "resisting high impedance" :)
ent.vhdl:
```
library ieee;
use ieee.std_logic_1164.all;
enti…