-
I am trying to create a custom instruction by combining the semantics of add,sili and srli but I have no clue where to find the semantics of these RISCV instructions. Can someone please help me out wi…
-
Hi Senmao, thanks for providing the code of your great work, it's really impressive and inspiring. I wonder if you can provide some instructions on how to suppress the objects or object semantics duri…
-
The semantics provided for the SDIV instruction trigger undefined behaviour on INT_MIN / -1.
For example, 010cc19a sdiv x1, x0, x1 gives us something like:
```llvm
%4 = load i64, ptr %X0, align 8…
-
Hi,
I am integrating Kimera-PGMO and Kimera-Semantics with a setup that successfully runs the front-end, back-end, and single-robot VIO, as shown in the attached image. However, I've encountered issu…
-
It seems this repo is out of date and the author may not intend to maintain this repo.
Could we maintain the intel instruction semantics in one fork of this repo?
-
[Job](https://mihubot.xyz/runtime-utils/81ee6aa5d4124c69b7a1425b348b82fd) completed in 31 minutes.
### Diffs
Diffs
```
Found 372 files with textual diffs.
Summary of Code Size diffs:
(Lower is b…
-
**Describe the bug**
Memory requests with acquire and release semantics are not handled correctly when using ARM + O3 CPU model.
Load-acquire instructions such as LDAR and store-release instruct…
-
We are getting some counter intuitive behaviors related to non-atomic accesses and rmw.
Consider this example
// Both read-modify-write instructions read the value stored by a non-atomic write ins…
-
When developing python code for Kontrol, you usually may need a custom pyk or evm-semantics to run against. To do this, you need to modify `pyproject.toml` to point at the custom version.
In partic…
-
if we do `push rsp` operand info tells us that we push `rsp` to `[rsp]` however, it should be `[rsp-8(size)]`.
https://www.felixcloutier.com/x86/push
```
IA-32 Architecture Compatibility ¶
For …
NaC-L updated
2 weeks ago