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![image](https://user-images.githubusercontent.com/24381042/105638961-fe65a600-5eb8-11eb-8f64-23e3cc9f5646.png)
i wanna check ip-xact file but error is occur
help me!
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@olofk, I am very interested in this project for my job as we would like to perform IP-XACT parsing and then make appropriate transformations.
I just wanted to know whether this is actively maintaine…
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I have some IP-XACT from some IP that is using expressions of the form:
('ffffffff) / $pow(2,0) % $pow(2,32)
This is a quite strange yet effective way of doing this but it comes from converting …
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Hi,
What IPXACT xml tag is mapped to the hdl_path of a component? For example, I have an IPXACT file that one of its field supposed to have hdl_path, which is described in "pathSements" field, but …
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Currently, we have a couple of purely structural Verilog files in OpTiMSoC: the toplevel files at various levels of the hierarchy. Creating these files is tedious and error-prone (getting wiring wrong…
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For exemple, Xilinx and Altera have their own file format to specify mapping between design pins and package pins (+ specify pin technologies, current, terminaison, ...)
It could be great to have a s…
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running 1.17.0 on debian via packages provided by the pgdg repository, from my understanding pgbouncer runs via systemd (and thus probably detects journald since https://github.com/libusual/libusual/c…
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Currently the hierarchy in librecores ends with "projects", which can be HW or SW or combined works.
We should introduce "IP Cores" (or named similarly) as a subhierarchy below a project (1:n).
Desi…
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Hi, I've passed the C simulation and C synthesis, but it took too long time(about five days) to finish the C/RTL cosimulation. So I dropped the cosimulation and wanted to export the RTL , but now I g…
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I am working on the remote file translator, specifically on IP-XACT currently. I don't see a way to model some of the address block attributes such as `range` and `width`.
~~~xml
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