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Hello everyone,
The error I get when running wally-toolchain-install.sh is this:
![image](https://github.com/user-attachments/assets/f3186df6-972a-4fc6-a4e9-b5ab99526b1e)
Has anyone came across…
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The [xPack RISC-V Embedded GCC](https://xpack-dev-tools.github.io/riscv-none-elf-gcc-xpack/) toolchain uses the `riscv-none-elf` triplet.
If you agree, I would like to contribute a small pull reque…
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On https://github.com/SymbioticEDA/riscv-formal there's a Table of Contents that gives good information, but I have a new RISC-V CPU I want to try to test and need to know the procedure to create a fo…
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### Creating this issue to list the items which should have same format across the specification. Lets keep updating this list here as we find them.
1. Use of `application processor` instead of AP.…
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Hi there, as I can see current riscv profile is mainly for application processor, and there is not yet a profile targeting at mcu market, maybe a mcu profile could be set, for mcu, interrupt should be…
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Hello team,
I have added the trigonometric instructions on riscv-gnu-toolchain. Now I am specifically looking for the steps required/process to compile my workload in Spike and Gem5 with these newly …
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We are designing [t1](https://github.com/chipsalliance/t1), which VLEN can be configured to be larger than 4K, in RISC-V Vector specification, The VLEN can reach to 64K:
https://github.com/riscv/risc…
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Hi,
when trying to make riscv-spike it's giving me a message that arch/boot.S is missing encoding.h
I know that FreeRTOS_on_Mi-V_Processor/miv-rv32im-freertos-port-test/riscv_hal/ directory has a "e…
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**Describe the bug**
The checkpoints are malfunctioning.
**Affects version**
Commit bae34876780dfb2bc22b9151bfda1d39ee80cfb1 (HEAD -> stable, tag: v23.1.0.0, origin/stable, origin/HEAD)
**gem5…
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This project seeks a set of Ghidra import regression tests to validate sensible behavior after importing executable binaries into new versions of Ghidra. It's morphed somewhat into generating newer e…