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**Describe the bug**
A thread is never executed when attempting 3 threads on 2 harts using RV32I ISA. The test passes when there are 4 harts or when using 64-bit ISA.
**To Reproduce**
cd thread…
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Hello everyone,
I compiled icicle RISC-V core for ICE40 FPGA https://github.com/grahamedgecombe/icicle It works perfectly with BlackIce II development board.
Now I would like to simulate the pro…
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Hi everybody,
there seems to be a typo on
- RV32I Base Integer Instruction Set, Version 2.1
- 2.5 Control Transfer Instructions
- Conditional Branches
in page 22.
This is …
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Recently, [MIT xv6](https://pdos.csail.mit.edu/6.828/2020/xv6.html) operating system is being ported to RV32I, and I maintain RV32I fork here: https://github.com/jserv/xv6-riscv
Is it possible to r…
jserv updated
4 years ago
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(attribution: AWaterman, edited )
FENCE is in the base ISA, but there is no test in the Base ISA test suite for it.
For compliance testing purposes on a uniprocessor, all you can do is check that …
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`valid_rs1` and `valid_rs2` are never read in the RISC-V example. Making sure that the values really correspond to `rs1` or `rs2` instead of stalling whenever at least one of them is associated with s…
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I noticed that the `getFields` function of the RISC-V example often gets called just to get the value of a single field (with calls along the line of `let funct3 := get(getFields(inst), funct3)`). Sin…
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in this section. a new phrase "may not be supported" is introduced. shouldn't it be unsupported optional?
==== RVI20U32 Mandatory Base
RV32I is the mandatory base ISA for RVI20U32, and is littl…
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I found a rather interesting/intriguing disparity between two systems when working with SweetAda and building the RTS.
Here is a clean SweetAda clone (master) running on Debian/aarch64 with the sys…
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~/caravel_board/firmware/mpw2-5/blink$ make clean flash
rm -f *.elf *.hex *.bin *.vvp *.vcd
#/usr/bin/riscv32-unknown-elf-gcc -O0 -march=rv32i_zicsr -Wl,-Bstatic,-T,../sections.lds,--strip-debug -ff…