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Viits HLS fails for the second example in docs/source/overlay_design_methodology/overlay_tutorial.ipynb, old Vivado IP cannot be used with new Vivado since 2020.2, and bitstreams generated using older…
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refer to petalinux 2019
- https://github.com/konosubakonoakua/blog/issues/97#issuecomment-2374149784
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Hi, I've passed the C simulation and C synthesis, but it took too long time(about five days) to finish the C/RTL cosimulation. So I dropped the cosimulation and wanted to export the RTL , but now I g…
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windows 10
vivado hls 2019.1
xfopencv 2019.1
demo : xfopencv\HLS_Use_Model\Standalone_HLS_Example
**simulation、synthesis is ok,but Co-simulation is error:**
`Starting C/RTL cosimulation ...
…
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Hi @jingpu ,
I have an error when I try to synthesize the C HLS using Vivado HLS 2016.4.
It seems that when compiling with `std=c++0x or std=c++11' causes this error.
> `Pragma processor failed…
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When I do “make all”, I seem to get the same error on HLS ip cores as seen below.
WARNING: [Vivado 12-3523] Attempt to change 'Component_Name' from 'axis_256_to_64_converter' to 'axis_256to_64_con…
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canny_edge_detection algorithm simulation and synthesis run without error but c/RTL simulation shows error
Starting C/RTL cosimulation ...
C:/Vivado/2019.1/bin/vivado_hls.bat C:/Users/Admin/AppData/…
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I am using Vivado and Vitis 2024 with an Arty Z7-20 board.
When I run the second or third steps of the single cycle implementation, I get 1 fetched and decoded instructions instead of 14. I saw one…
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I am running an Ubuntu virtual machine (Ubuntu Desktop 18.04 LTS and have installed Vivado 2019.2. I have created a python environment and have installed conifer using `pip install conifer`.
Howeve…
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I have a qkeras model. When I load model(load_qmodel) and I want to compile it I get this error.
I installed the last version of HLS4ML libarary.
**Code:**
model_path = 'weights-chkpt-11-0.65767…