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Xilinx has released Petalinux 2019.1, and Petalinux 2018.3 is been around for a while now. What needs to be done to build this for the new version of Petalinux? What is different from official Xilinx …
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Please add support for Vivado 2020.1 and the newest petalinux SDK.
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I followed the "Zybo z7-20 revision Platform" README and I am stuck at the build section for the sample project. When I go to build the project I get the following errors:
![error_snip](https://use…
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Hello, I'm trying to build PYNQ image for my Zybo Z7-10. As shown in the [link](https://discuss.pynq.io/t/3rd-party-images-for-zynq-boards/431) I'm using your projects. I would like to build PYNQ 2.5 …
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I'm new to ESP and heterogeneous SoC design as well. I'm very interested in using ESP for our research project.
But we don't have any supported boards now.
We would like to use ESP for the Ultra96…
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I would like to contribute and create a defconfig for the zybo z7-10 board - where to begin?
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Sorry about this, I don't have any other way to contact you. I'm trying to write the firmware in SDK for the PS in a similar design based on your HLS code. I configured the DMA as SG and I am using t…
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On which board this code is targeted.........?
ultrascale zynq or only zynq..........?
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Hi,
I am facing a problem when i build vector addition application project. I can build with Emulation-SW, but when I tried to build with Emulation-HW or Hardware. I got the error:
ERROR: [v\+\+ …
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Could this project add Xilinx Virtual Cable Support? JTAG and programming are very solid in this project, found some other XVC project, like https://github.com/kholia/xvcpi and https://github.com/Berk…