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https://python3statement.org/
Many major projects including pytest, ipython, pandas and numpy are dropping Python 2 support.
We can simplify some of our code, and explore Python 3 only features …
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**Type of issue**: other enhancement
EDA Playground (https://www.edaplayground.com/home) supports quite many HDLs, including SystemVerilog, UVM!, and MyHDL. I is a very easy way to play with code s…
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Is there any way to add clocks generated with ecppll to ghdl? Is there any other generator? Is there any examples somewhere?
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I would really appreciate a feature to maintain variable naming post-compilation to VHDL or Verilog like MyHDL. As of now the code that clash outputs is very difficult to read or reason about its conn…
ghost updated
4 years ago
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The second one is https://github.com/fukatani/awesome-hdl
Can you please merge it?
Or is there any replacement?
Nic30 updated
4 years ago
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Hi,
I'm trying to create a VVC for 10GBASE-R. However, it requires a continuous tx-output (and continuous parsing of rx-input) for the encoding to always be correct. I would think this would be pos…
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Hi @rodrigomelo9,
This type of project seems like it would be an excellent addition to the SymbiFlow project. Did you want to join forces here?
The rest of the SymbiFlow project is using the fol…
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I'm trying to implement a protocol that requires me to assert the CS line for a few milliseconds without transferring any data.
The Windows-based tool that I'm trying to replicate makes calls to `F…
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In Heptapod by bitbucket_importer on Jun 10, 2011, 10:50
*Created originally on Bitbucket by [benallard (Benoît Allard)](https://bitbucket.org/[7.3.7](https://github.com/gitlab-importer/pypy/mileston…
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* [done] VHDL will get new full 2008 grammar
* [done] all AST object will have own class defined in Python and instantiated by C++ (JSON conversion will disappear from C++)
* [done] AST and HD…
Nic30 updated
5 years ago