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This may be related to the other issue I opened concerning PhysicalNetlistExample. However, I have more information on this one.
The exception is cause by `n.getDevice()` returning null on [line 35](…
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Here are some issues I found while testing the verilog parser.
If you wish to split the work on these ones, just tell me and I can seperate them in different threads. Moreover I'm not 100% sure, if …
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I'm on rc3 -
The `yosys_rewrite_verilog.tcl` step of this flow is taking a strangely long time. yosys is consuming ~92 GB of RAM and has been spinning a core at ~100% for 16.5 hours.
The comman…
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Here are already some issues I found while testing the verilog writer (**src/hdl_writer/hdl_writer_verilog.cpp**). Some others may follow after the testing with the new verilog parser. Also there are …
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Take a structural netlist (generated by vivado for now) and parse it into our netlist format. This will likely involve creating a tokenizer and a resursive decent parser similar to what we have done w…
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**Describe the bug**
I'm trying to follow the steps mentioned in the [OpenROAD documentation](https://openroad.readthedocs.io/en/latest/user/BuildWithDocker.html) for **Building from sources using do…
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**Describe the bug**
When parsing an incorrect VHDL netlist, with empty port maps of gates HAL crashes.
**Expected behavior**
hal should print an error and continue working.
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I tried out the demo on the project website. It is such an eye candy! Thank you for sharing this project.
The only catch is that I am not using Kicad to design my PCB. I wonder how can I modify you…
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#### Expected Behaviour
Localparam is in place so it can not be overriden by deparam, additionally it should define a parameter.
#### Current Behaviour
When using localparameter, odi…
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Hello, how feasible is it to generate a netlist from a SpiceSharp Circuit? Is this already implemented? It would seem to be just a matter of iterating through all the Entities of the circuit and print…