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Hi there, not an issue more of a question.
Currently for formal verification SymbiYosys and Verilog/SystemVerilog are used. As documented [here](https://spinalhdl.github.io/SpinalDoc-RTD/master/Spi…
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I stumbled upon the following error when following https://github.com/SpinalHDL/VexRiscv/tree/master?tab=readme-ov-file#murax-soc using Verilator 5.028:
```
$ make clean test
error: #error "Verilat…
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Hi,
Great update to the readme - thanks.
Out of curiosity, I've been playing with the latest version and wanted to find the max I can do with an 85k Ulx3s board.
Mainly I wanted to see how man…
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I just want to report some unused flip-flop registers. They got removed during elaboration and since they are never used, they could also be removed?
We should discuss how to handle these.
I found…
dnltz updated
5 years ago
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initialContents is not sufficient: it still requires way too much knowledge of Scala to simply load a binary file.
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https://www.embench.org/
> Dhrystone and Coremark have been the defacto standard microcontroller benchmark suites for the last thirty years, but these benchmarks no longer reflect the needs of mo…
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```scala
class InOut extends Component {
val b = new MyBlack
val a = new MyBlack
val c = new MyBlack
val ret = Analog(Bits(2 bit))
b.io.x := ret
c.io.x := ret
a.io.x := ret
}
…
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Hello, I am new with both SpinalHDL and RISC-V. I have compiled Murax Soc using internal RAM on Arty7 and they work well. Now I want to use external SDRAM DDR3, I try to edit the Briey.scala as follow…
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Hi, I am new to SpinalHDL.
I wonder if this is a mistake on https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Examples/Intermediates%20ones/uart.html#implementation:~:text=%3DUartCtrlInitC…
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VexRiscv implements a simple MMU. This MMU is effective, but nonstandard, and requires extended instructions to do refilling.
Would it be possible to give a simple example of how to use it? For e…