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**What is your question?**
DISCLAIMER: This is a question and suggestion. let me know if you want me to seperate the suggestion into a seperate issue for tracking my feature request.
I actively us…
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I am just beginning to review the VHDL version,
please could this expression be elaborated?
ie is this a defect of the implementation?
or what is the reason for its inclusion?
It has been applied …
peepo updated
2 years ago
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We are not sure if we have the right VHDL source code version for the firmware we are using to run the Test Bench.
- We have one version of VHDL source code but
- we are not sure how to compil…
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Synopsys VCS-MX supports not only (System)Verilog as is the case with the backend right now but also VHDL, allowing mixed-language simulation.
Some pointers:
- http://www.vlsiip.com/vcs/
- http://s…
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I only know Verilog well enough to comment on it, but I know VHDL would benefit from this, too.
In Verilog numbers written default to decimal, but if prepended by 'b or 'h the number is binary or h…
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When installing from the cargo crate, using `cargo install vhdl_lang`, `vhdl_lang -c vhdl_lang.toml --perf` failes with the panic message
```
thread 'main' panicked at 'Couldn't find installed lib…
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## Problem
There is no Major for any HDL(Hardware Description Language)s as I see it.
Like VHDL, Verilog and SystemVerilog.
## Solution
Implement Major modes for HDLs?
## Alternatives
Develo…
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This would greatly help with simulating mixed-language projects, which could look like the following:
Verilog testbench (which should be possible now):
1. Use yosys to synthesize the modules (whic…
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I suggest that you should rename it into something like vhdl-lsp or vhdl-rust-lsp.
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As an addendum to this issue: https://github.com/VHDL-LS/rust_hdl/issues/298
If one doesn't use/set the object (port, signal, variable), VHDL-LS correctly flags a warning that it's not set - all good…