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**Description**
https://github.com/ghdl/ghdl/blob/master/scripts/vendors/config.sh doesn't have the "bash" interpreter shebang line, which would cause it to break when the current shell is not bash.
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Hi,
What is your estimate of supporting 64 bit RISC-V. I'm still pretty new to this, Could it run 100mhz on an Artix board? Would it even fit?
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Hi @esar ,
So i think I can fellow the v3 hdmilight.
Now for FPGA I can use xilinx ise got the fpga/HdmilightTop.bit
and what is the next steps?
When got the v3 hardware, Plug into PC usb an…
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Hello, I tried to build the jedec with ise 14.7 webpack.
But my jedec differs a bit from yours.
Would you please provide the complete ise project folder...
I bought a xilinx jtag programmer (jtag…
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Verilator 4.109 devel rev v4.108-9-gab5d4bd5
Running `verilator --lint-only --Wall` for the code below:
```systemverilog
`default_nettype none
module pwm #(dutyBits = 2) (
input
wire [d…
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IP generators such as Xilinx Coregen produce VHDL wrapper files for simulating the core. Memory initialization files (.mif) which contain the initialization vectors are generated for certain cores, fo…
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**Description**
Some yosys backends do not use separate user-constraint files (LPF) to map pins to ports. The "traditional" method of creating user constraints for these backends is to use an attribu…
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Hi,
I try to compile Xilinx Vivado libraries on PC running Windows 10.
Vivado 2018.1 is installed and fully functional.
Change directory to `\lib\vendors`
Have set in `config.psm1` the setting…
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Hi Sylvain,
Do you have a list of the panel driver ICs supported? I know it's working fine with ICN2037/ICN2012. Is ICN2038 or ICN2038S supported? It'll be nice to have a short list of the major dr…
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Hi. I am not sure about to post it here or at the Yosys repo, but a first glance, it seems related to deal with VHDL packages. Let me explain.
* I was adding `ghdl-yosys-plugin` support into [PyFPG…