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You have an idea about possible improvement(s) to the project but this is difficult to know if this is realistic or how much work it could be involved, please use this issue to share your idea and dis…
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Is there a way to change the clock freq of the bootloader for the icebreaker bitsy?
The original design has a 12Mhz Clock built in, my custom design uses a 40Mhz Clock.
Does this influence the USB …
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## Steps to reproduce the issue
Hello! My design at https://github.com/jay20162016/fomu_async is not working again.
Uncommenting the line with the "works" comment (and commenting the "doesn't work" …
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Hello,
I've been trying to run some software examples on a Fomu.im board. After some experimenting i realized that the neorv32_uart_print() outputs were missing. After some debugging i realized tha…
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Please Note (click to expand)
Suggestions that don't match this template will be closed. We understand this can seem harsh, but in order to ensure we are able to keep on track of bugs other serious…
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Good first issue...
% `python3 -m pip install codespell`
% `codespell --ignore-words-list="gameboy,iif" --quiet-level=2`
```
./wasm3/README.md:76: predictible ==> predictable
./wasm3/test/run-spe…
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Hello, I'm trying to test software which uses fpga as coprocessing unit. This development is based in a ZynqMP+ which shares the RAM between the FPGA and multiple CPUs in a common axi bus.
So, the…
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During experiments to synthesize the project with GHDL & Yosys I found that the Watchdog timer unit cannot analyzed when VHDL-08 standard is used. The record type for the control register uses the now…
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Hello! My design at https://github.com/jay20162016/fomu_async is not working again.
Uncommenting the line with the "works" comment (and commenting the "doesn't work" lines) makes it work.
Similarly…
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Rather than a feature request, this is a topic for discussion. It seems that [riscv/riscv-arch-test](https://github.com/riscv/riscv-arch-test) might be handled as a submodule in subdir `riscv-arch-tes…