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Hi,
I'm really enjoying this wrapper around myhdl as it seems more intuitive to me. I've been having some trouble with the Peeker.to_wavedrom function for long simulations (unable to get horizontal…
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character literals ('0', '1', 'Z' etc) are converted to an integer in line 176 of src/vhdlConvertor/literalParser.cpp by subtracting the value '0' This produces 'weird' results for anything else than …
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Summary
## System information
```
MyHDL Version: 0.10
Python Version: 3.7
```
Myhdl source files `_always_seq.py` and `_toVHDL.py` use the new reserved keyword `async` as identifier. I had to …
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I have installed pyFDA 2.0.2a using the mentioned methods. Program launches with pyfdax command, but Plot Tabs are not displayed. I have tried several times, both after cleaning the cashed repositori…
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I am testing out MyHDL using the implementation of a simple 8 tap FIR filter. I am uncertain if this is a bug or a mistake on my part, but I followed the readthedocs conversion example as closely as I…
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Summary
```
import myhdl as hdl
@hdl.block
def MyExperiment():
clk = hdl.Signal(0)
@hdl.always(hdl.delay(1))
def drive_clk():
clk.next = not clk
@hdl.alway…
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Hi Christian:
I am getting the following output when I try to generate a HDL verilog file.
mikek@mikek-MSI:~/Documents/SDR_Radio/pyFDA/pyFDA_github/pyFDA$ python -m pyfda.pyfdax
Created logging…
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Do you have a forum?
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There's a minor syntax error that occurs when byte-compiling `fixpoint_widgets/filter_iir.py`, because the `ResetSignal` function from MyHDL has a keyword argument called 'async', which is a keyword i…
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I'm doing quite a bit of cosimulation with MyHDL and iverilog. I am running in to issues with truncated or invalid LXT2 files. This seems to be happening when the cosimulation ends early due to a fa…