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Hi,
I pulled commit da3a1003019e31fb8cf8089bb568b093486a23c2
now, I cannot run the regression tests any more. it seems the subunit.py file is not included.
Best regards,
Bob.
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**Describe the bug**
During detail routing am facing below issue
```
[INFO DRT-0165] Start pin access.
[INFO DRT-0076] Complete 100 pins.
[INFO DRT-0076] Complete 200 pins.
[INFO DRT-0076] …
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**The bug**
The following error message shows up during the floorplan step and the flow fails:
```
[INFO PDN-0012] **** END INFO ****
[INFO PDN-0013] Inserting stdcell grid - grid
[INFO PDN-0…
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Hello,
Following instructions fails with magic exit code -9
Multiple lines spamming "No label found with index ." in log
It blew my log file to about 50GB so I cant copy and paste it here.
I r…
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Needed by the skywater-pdk to do LVS checks (also needed by OpenRAM).
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So far I think we have got our bearings on how to use the distributed block RAMs on the FPGA. However, there are also larger memories available. Now going through the process of ASIC hardening and mod…
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It would make sense to write the assumed frequency next to the power numbers in the report.
As far as I can tell, these are for 100 MHz as stated in the `tech.py` file using the `default_event_fre…
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Thank you for the work that you are doing. A question: for the Skywater-PDK, do free SRAM compilers exist that support the OpenROAD flow? VLSIDA/OpenRAM does not appear to support Skywater and I see t…
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commit: b3e249c722d33
although overriding the drc/lvs/pex tools to calibre, it still errors on: ERROR: file globals.py: line 253: magic not found
If I insert print statements before, it prints 'ca…
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Hi! I'm using this library with an ST7796S LCD display, but there's an issue with the drawing of the images:
![IMG_20210216_125944](https://user-images.githubusercontent.com/57992871/108061043-077d09…