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It is not really an issue, but rather a proposal for an extension :
https://github.com/laurentc2/SKY130_for_KLayout/tree/main/redundant_vias_insertion
Laurent
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Observations:
- Prematching flattens cells that don't have a match in the other netlist. This may cause long run times when comparing fully extracted layout to blackbox srams, for example. *Proposal:…
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We are facing several issues with the device models. We have summarized some of them in the following repo:
https://github.com/mabrains/sky130_analog_testcases/tree/master PFET Vth is incorrect mos…
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The analog pad (as well as other pads) provided as part of the skywater 130 pdk contains DRC errors
Steps to repoduce:
- Install magic rev. 8.3.399
- Install the skywater pdk using open_pdks rev…
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The Verilog-A model does a manual integration of the filament thickness here:
https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/blob/6574676cbbd062d63be0f090013d59ced7302349/cells/rera…
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## Expected Behavior
The .lef file should load without any issue on Innovus.
## Actual Behavior
I am getting an error on Innovus when loading the .tlef file (_skywater-pdk/libraries/sky130_fd_sc_…
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When I extract the netlist from a `.mag` layout block which has been generated in SKY130 using `OpenLane`, and I use `netgen` to compare it to the powered Verilog netlist, then it fails by default due…
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If the intent was to follow the standard used by the sky130 PDK, then this is an epic fail. It needs correcting on multiple fronts.
For starters, the standard cell verilog modules make references …
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### Description
Following a tutorial I got an error in interactive mode. Any step of a tutorial which requires an interactive mode do not work.
### Expected Behavior
On the command
```
or_gu…
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This appears to come from using an old magic techfile? The latest tech file defines these devices as "sky130_fd_pr__res_generic_nd__hv" and "sky130_fd_pr__res_generic_pd__hv". ngspice will not simul…