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Hello,
I am working on the lowrisc `frame-buffer` branch and trying to understand how the VGA peripheral works. My initial objective was to increase the VGA resolution, so I started looking at the `p…
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make upload命令是将应用程序下载到flash的基地址么?
这么做难道不会覆盖已经在flash中的mcs文件么?
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**Describe the bug**
I'm trying to compile a simple SDFG for an Intel FPGA, however I'm getting the following errors:
```
/usr/include/CL/opencl.hpp: At global scope:
/usr/include/CL/opencl.hpp:…
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if I intergrated nvdla into FPGA successfully , can I just run "nvdla_runtime" to start inference with the FPGA conncted to hostPC ? is this feasible?
Or, is nvdla_sw only designed for simulation ??…
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Post here ideas with affordable cameras, image sensors, lenses, image processing boards, to build an open source large scale deployable smart camera.
We need to test a lot of options, eBay, Aliexpr…
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Hi,
I noticed your extended CEDR on RISC-V Heterogeneous SoC Design. I wonder if the RISC-V integrated CEDR source code along with the FPGA image is available? I hope to conduct some DSE experiment…
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@shenki has had the repl loop working in QEmu.
@mithro has had the repl loop working on Opsis hardware.
@Kathatosada got repl loop working on the MimasV2 at Linux.conf.au
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i want to run keystone with CVA6 as processor and working on xilinx S7-SP701 FPGA board.
SDK git from : https://github.com/keystone-enclave/keystone.git ,and work on orange/master.
build steps fo…
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Hi!
I finally got myself to trying my luck with my ali m3801 board, which grabbed my interest because of its potential use for software radio (my board includes a digital tuner IC has no public dat…
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Hi,
my goal is to eventually run a configurable nv_small on Zynq Ultrascale+ while using an nvdc compiled caffe model for inference. I am still a novice in the field of FPGAs, NNs, etc. and have some…