SI-RISCV e200_opensource issues

SI-RISCV / e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

https://github.com/riscv-mcu/e203_hbirdv2

Apache License 2.0

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issues

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Where is the waveform file ? (.vcd)

#50 jasonlee1001 closed 3 years ago
1
关于在 Verilog TestBench 中运行测试用例

#49 saltanat3k opened 3 years ago
1
关于蜂鸟的RISCV处理器支持向量扩展的问题

#48 WilliamWangPeng opened 3 years ago
0
Fix conditional operator in e203_exu_alu_muldiv

#47 sylwpro opened 3 years ago
0
mcs和bit文件生成位置错误，并且无法使用

#46 DeltaEnvy opened 3 years ago
1
请问怎么把benchmark编译成$readmemh可以读入的文件呢

#45 Toxic-Scofield opened 4 years ago
0
原生tb仿真报fatal

#44 Toxic-Scofield opened 4 years ago
1
e203_itcm_ctrl 模块里面访问优先级顺序

#43 qian-gu closed 4 years ago
6
Is the source code of E205fd available? where can i find it

#42 lactusec opened 4 years ago
1
使用 iverilog 仿真會卡住

#41 jasonlee1001 closed 4 years ago
4
vsim/Makefile: fix build command in some case

#40 vowstar opened 4 years ago
0
MCU应用程序存储位置疑问

#39 EECScat opened 4 years ago
1
icb接口模板

#38 Shell-picking opened 4 years ago
0
Testbench error

#37 xiaoliyang1 opened 4 years ago
2
failed in riscv-tools/riscv-tests/isa/generated/rv32ui-p-addi testcase

#36 jackfan00 opened 4 years ago
0
此系列处理器是存储器映射I/O，还是端口映射I/O?

#35 lactusec opened 4 years ago
0
蜂鸟E200和Freedom E310内核区别

#34 EECScat closed 4 years ago
2
oooooooo

#33 xiaojia102003 closed 4 years ago
0
源码问题（gpio模块）

#32 Shell-picking opened 4 years ago
2
使用 axi_ready 作为 axi_valid 的生成条件

#31 ljgibbslf opened 4 years ago
1
Define CSR Address width

#30 howard0su opened 4 years ago
0
Fix typo in decoder

#29 howard0su opened 4 years ago
0
Fix combination loop in icb_claim_irq and icb_complete_irq.

#28 xxqfhj opened 5 years ago
0
sirv-e-sdk目录下的Makefile脚本如何输出elf和hex文件？

#27 xiaojia102003 closed 4 years ago
3
make upload以及程序下载问题

#26 clx782782 opened 5 years ago
7
Can I use prebuilt_tool to compiler the code for e203 on broad?

#25 listen1116 opened 5 years ago
1
环境设置

#24 wangjiayu0116 opened 5 years ago
1
编译错误

#23 zhuzhizhan closed 5 years ago
1
如何通过设置plic把电平中断变为脉冲中断。

#22 245950258 opened 5 years ago
0
RAS（return address stack）

#21 AlexChenzixuan opened 5 years ago
1
English language toolchain host

#20 SKuRGe911 closed 5 years ago
3
一次硬件中断被响应多次

#19 rsthnn opened 5 years ago
3
can e200 Can E200 SoC be implemented on zcu102 or 104

#18 tangchuanchuan opened 5 years ago
1
A failure when running Verilog simulate testbench

#17 JianNingZhang opened 5 years ago
3
olimex的连线和 udev设备识别

#16 zhangshuai-neu opened 5 years ago
7
RISC-V ToolChain's link is empty?

#15 zhangshuai-neu closed 5 years ago
0
Why I can not find the website of 芯来科技 from google

#14 watershade closed 5 years ago
3
Typo in prebuilt_tools/README.md

#13 rockrush closed 5 years ago
0
关于e200_opensource协处理器模块EAI

#12 albertcity closed 5 years ago
1
English language documantation ?

#11 luudee opened 5 years ago
0
DTM NOP overwrites a word in Debug RAM

#10 brabect1 opened 5 years ago
0
compare with SiFive-E21

#9 zhouqinghua opened 5 years ago
0
Verilator testbench for ISA tests

#8 brabect1 opened 5 years ago
0
Can E200 SoC be implemented on Zedboard or Virtex-7?

#7 clx782782 closed 5 years ago
5
Missing some reference in the design

#6 TonyWu78 opened 6 years ago
1
The module Description of e203_lsu.v is same as e203_lsu_ctrl.v

#5 lyxnevermore opened 6 years ago
0
submodule request

#4 sequencer closed 3 years ago
0
Submodule patch

#3 sequencer closed 5 years ago
0
端口名后缀

#2 kezhou2 closed 6 years ago
1
supporting part of RISC-V instruction set? Which part?

#1 poweihuang17 closed 6 years ago
5