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Hi. We (@eine) were testing mixed synthesis cases.
* Verilog + VHDL (top) works (note: the Verilog module must be specified as component into the VHDL).
* VHDL + Verilog (top) works when generics …
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[VHDL/pyVHDLModel](https://github.com/VHDL/pyVHDLModel) is an abstract language model for VHDL, meant to be used as an interface between *any* VHDL parser and projects providing graphical views, refor…
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Currently, there are errors in the VHDL code that cause a crash in GHDL, which will soon be fixed, but the errors will still remain. See https://github.com/ghdl/ghdl/issues/2334.
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This is a proposal: let us make ChiselVerify a more generic testing tool also for Verilog and VHDL designs. Something like, but better than, cocotb.
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A VHDL simulation initializes value of signal to `type'left`.
This may sometimes hide bugs on RTL, that later pop-out on GLS.
An example is FSM coded with enum type and first state being `S_IDLE`.…
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**Is your feature request related to a problem? Please describe.**
I'd like a rule to enforce case on the `others` keyword in selected assignments. For example, I'd like
```vhdl
architecture rtl of…
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Hello, do you think one day symbolator could be used to parse one or more VHDL files to generate a schematic of the instanced components/wires?
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I read the documentation but I'm not sure about how I should use that setting.
For example, in my VHDL code I have some `use IEEE.STD_LOGIC_UNSIGNED.ALL`.
I have the Synopsys source file, but I …
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Some package files under **https://github.com/VUnit/vunit/tree/master/vunit/vhdl/*** have inconsistencies in their package name and file name. So there is a need to modify the file names of such VHDL …
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When attempting to build a design with the `IEEE.FIXED_PKG` package in vivado, the following errors are thrown:
```
chk-syn | CRITICAL WARNING: [HDL 9-3134] 'fixed_pkg' is not compiled in library 'i…