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Hello SweRV community! :wave:
It would be great to add some relevant GitHub topics to this repository. It may bring more people and help with promoting this core as well as related open-source stuf…
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Issue Type: Bug
Open an existing file via Explorer from a network-mounted drive (such as "\\\\xsjswsvm2\mpmc\sandboxes\jeffs").
File > Save As fails to open the browser window in the folder where …
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Hi @Nic30
I find that the 'protect will cause the error of parser.
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## Information
**VIM version**
Neovim v0.5.0-675
Operating System: Windows 10
## What went wrong
I installed the ale plugin with vim-plug. I have flake8 (python linter) installed.…
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The circuit database has to be somehow implemented in every project related to HDL/FPGA etc.
This leads to ridiculous amount of work for developers of such a libraries and also makes this libraries i…
Nic30 updated
4 years ago
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Milestone: https://github.com/cocotb/cocotb/milestone/11
Release process checklist:
- [x] Close all issues blocking the milestone
- [x] Prepare release announcement email
- [x] Tag a release
- …
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I like the new `toVerilog` and `toVhdl` implementations based on running the Python classes through `toJson`. Just to be clear, here is my current understanding of the parser chain.
Current:
HDL…
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**Type of issue**: other enhancement
EDA Playground (https://www.edaplayground.com/home) supports quite many HDLs, including SystemVerilog, UVM!, and MyHDL. I is a very easy way to play with code s…
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Hi @rodrigomelo9,
This type of project seems like it would be an excellent addition to the SymbiFlow project. Did you want to join forces here?
The rest of the SymbiFlow project is using the fol…
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I have a design that has a clock with a period of 10 (in default cocotb units), and a simulation that runs for 8508 cycles. What I see in the report for VCS is the following:
```
*****************…