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if I intergrated nvdla into FPGA successfully , can I just run "nvdla_runtime" to start inference with the FPGA conncted to hostPC ? is this feasible?
Or, is nvdla_sw only designed for simulation ??…
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# Bug Report
## One-Line Summary
Unexpected behavior for clock configuration.
## Issue Details
### Steps to Reproduce
* First confirm that some clock options do work.
* ``` $ a…
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Post here ideas with affordable cameras, image sensors, lenses, image processing boards, to build an open source large scale deployable smart camera.
We need to test a lot of options, eBay, Aliexpr…
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Hi.
I just started with migen/LiteX and FPGA.
I want to add an UART to colorlite.py
So I copied and modified the parts from ios_stream.py. Sending four bytes over UART works fine. But it keep on …
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Hi!
I finally got myself to trying my luck with my ali m3801 board, which grabbed my interest because of its potential use for software radio (my board includes a digital tuner IC has no public dat…
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### Version
Yosys 0.24+10 (git sha1 69cbef966, gcc 12.2.0 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fPIC -Os)
### On which OS did this happ…
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- [ ] Make a chapter4.md file
- [ ] Create a summary in the .md file
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It would probably make sense to have a separate project for such an exporter, for now I just wrote it down so I don't just forget about it. CircuitPython has some concept of a register map, with some …
jeras updated
11 months ago
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somhi updated
2 years ago
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i want to run keystone with CVA6 as processor and working on xilinx S7-SP701 FPGA board.
SDK git from : https://github.com/keystone-enclave/keystone.git ,and work on orange/master.
build steps fo…