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Hi,
Thank you for your hard work on OpenRAM.
We are using your tool for the generation of a single-port cache tag storage with quite unusual specifications (25-bit words with usual 8-bit bytes)…
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In calibre pex mode, the timing cannot be executed correctly:
the measurement statements in the stim.sp file, ran on the pexed file do not work:
for instance: tran v_bl_READ_ZERO0 FIND v(xsram_2_1…
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Dear,
I'm looking for a open source small OpenRom e.g. 256Words 16bit for a custom design.
Has OpenRam team worked on ROM or did the OpenRam team know the availability
I touth Aliance had done som…
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For mine application specific device I need a small ROM e.g. 256Word 16bit.
I have already seen RAM and Flash announcement but will there also ROM available ?
Is there already some information about…
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Thanks for a great tool!
I was just giving it a try and I found out that the example configs in the [compiler/example_configs](https://github.com/VLSIDA/OpenRAM/blob/dev/compiler/example_configs/) …
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Hi, @mithro I am following your hard work here, and I don't want to bother you much but I was reading the README, and I couldn't find any mention of a memory generator and also of IO Cells. Do you kno…
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Hi All,
I am working on a 16-Bit processor I wrote many years ago (named Pico16) using the OpenLane flow. I am using the Docker image (downloaded last week) and have been able to get it all the wa…
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Hey everyone,
I have a problem with the specification of power/timing through the spice simulations. Regardless of the size of the generated SRAM, I get the following error.
`
Technology: scn4m_s…
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hi.
(sorry. my english very poor.)
1. my firmware scheme:
- read SD file -> copy to psram -> jpeg decode-> display lcd
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2. my test module …
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Dear Author,
When implemented the Ariane core in Silicon, the DC result shows that the SRAM area accounts for 94% of the total area. The synthesis time takes more than 20 hours. The SRAM I used is th…