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I'm playing with a program on the EH1 that ends up issuing a speculative data load, despite the PRM saying that EH1 does not do this.
Code snippet:
```
; Function finishing up
lw s11, 12(sp)
…
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Hi guys,
could you tell me which version of OpenOCD you've used while testing?
I receive the following error code:
Info : JTAG tap: riscv.cpu tap/device found: 0x00000001 (mfg: 0x000 (), pa…
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Hello SweRV community! :wave:
It would be great to add some relevant GitHub topics to this repository. It may bring more people and help with promoting this core as well as related open-source stuf…
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https://content.riscv.org/wp-content/uploads/2019/04/RISC-V_SweRV_Roadshow-.pdf
Page 11, it is said using optimized strcpy function we could get 2.9 DMIPS/MHz.
Where can I find the optimized ```st…
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As described in a recent paper on optimizing SweRV performance on Verilator (see under https://veripool.org/papers) there is a very large performance speedup when RV_FPGA_OPTIMIZE is set.
I would s…
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I am looking at exploring an ASIC RV32 implementation for area/power studies.
Would you have a document that describes your ASIC synthesis flow?
Since I am looking at academic work here, I have acc…
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@tgorochowik Travis found that the merge for #2223 breaks SweRV in the verilator_ext_tests when they try to compile, please investigate, thanks.
```
Vtb_top__3.cpp: In static member function 'stat…
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I am under the impression that these are only used during the very first and very last time steps per simulation. Yet, the settle block is 40% of the generated model code in SweRV EH1. Should we stick…
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@gezalore I've been looking at some internal code coverage issues and after cleaning up some false negatives, see only one uncovered in V3MergeCond.cpp:
160 AstNode* maskLsb(AstNode* no…
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sv-tests' third_party/tests/uvm is not a submodule.
Can we make it a submodule so that I and others can clone it for standalone Verilator testing etc?
Assuming you agree this makes sense, where…