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It seems that the problem is with the type in declaration: `wire [i:i] z = x;`
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In my SystemVerilog I have a union declared within a package - each entry of the union references a separate struct definition:
```sv
typedef union packed {
node_raw_t raw;
node_load_t l…
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This issue is to pursue propagating updates for Kintex7 to upstream. At this time, this seems to be only a couple of changes to Python scripts, cf. https://github.com/kintex-chatter/nextpnr-xilinx/com…
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I'm trying to filter-out nonsythesisable constructs in yosys. WIP branch can be found here: https://github.com/SymbiFlow/yosys-f4pga-plugins/pull/243
I'm using following test:
```
module dut();
…
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Can be related to: https://github.com/chipsalliance/UHDM/pull/618 / https://github.com/chipsalliance/UHDM/issues/603
When ``Compare`` function from ``UHDM::BaseClass`` is used to compare ``Class`` …
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TEST:
```
module dut;
PS7 PS7 (
.EMIOGPIOO (emio_gpio_o),
.EMIOGPIOTN(emio_gpio_t),
.EMIOGPIOI (emio_gpio_i),
);
endmodule
```
(Notice comma in line ``.EMIOGPIOI (emio_gpio…
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I think the build process could be simplified by using git submodules:
1. sudo apt install libftdi1-dev libudev-dev git cmake build-essential tclsh clang tcl-dev libreadline-dev flex bison python3-…