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Why?
Our setups, worked with 4.020, do not compile now! Please, don't remove/change command switch options in future, we have enough troubles with our design itself yet to deal with the tool upda…
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On certain designs, yosys errors out with the following
```
Note: Assuming pure combinatorial block at ./designs/src/swerv/swerv_wrapper.sv2v.v:75 in
compliance with IEC 62142(E):2005 / IEEE Std.…
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Hi,
I am trying to enable DMA for SweRV. I did following changes in **testbench/tb_top.sv**
1.added following signal
logic [31:0] dma_haddr;
logic [2:0] dma_hburst;
logic [3:0] d…
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Hi,
I successfully run the RISC-V Compliance check (https://github.com/riscv/riscv-compliance) on the provided SweRV RTL and I was able to pass most of the tests except the following:
1. ree_rv32i…
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I suggest that the SweRV repo add a "make benchmark", that runs a binary that e.g. runs CoreMark for about 30-60 seconds.
## Background:
I'm using Cores-SweRV as part of the Verilator regression…
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I see that CPU often checks for instruction data in icache even when it's disabled by SWERV configuration (icache_enable=0). This affects overall CPU memory access performance.
Please, suggest if it…
vit82 updated
4 years ago
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Hello - I am trying to run simulations of some large C programs on the SweRV RTL, but figuring out the expected initialization and finish functions, linker script and any other system configuration re…
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While working on #2257, I had a couple of ideas for general multi-threaded tracing. Currently we support `--trace-fst-thread` but that relies on a feature of the FST API.
One method for general thr…
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The Vivado synthetizer does not like the ' in
rden
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Hi,
i'm trying to change the location where the SwerV look for his programm to be compliant with my adress map. In your "Hello world" Example it loads his first instruction at the address 0x80000000,…