-
---
Author Name: **Shinobu TAKANASHI**
Original Redmine Message: 2334 from https://www.veripool.org
---
Hi all,
After 3 days struggling, I could managed to release the initial version of Verila…
-
I think this is a generally useful component that many kicad scripting tools could use, no point in every tool rewriting or copy pasting this stuff.
-
The git commands in the makefile don't work then.
I'm getting:
```
fatal: Not a git repository (or any parent up to mount point /home)
Stopping at filesystem boundary (GIT_DISCOVERY_ACROSS_FILESYSTEM…
ghost updated
7 years ago
-
Originally reported on Google Code with ID 79
```
What steps will reproduce the problem?
1. Use the following archive: http://www.eecg.utoronto.ca/~kmurray/titan/gaussainblur_netlist_inconsistency_er…
-
If the developers are amenable, I would like to write a plugin for exporting to gEDA PCB/pcb-rnd format.
This will make artistic, freeform board design, and importantly, gerber generation, much eas…
-
From Dave Evans:
> I've had a few issues with the blif parser like this where it just kind of breaks with an unhelpful assertion or segfault. In the future would it be possible to get some helpful er…
-
---
Author Name: **Satish S**
Original Redmine Issue: 1059 from https://www.veripool.org
Original Date: 2016-05-11
Original Assignee: Wilson Snyder (@wsnyder)
---
Hi. May I know if the comments a…
-
This seems the bit of spice that causes it:
```
.SUBCKT _paramod_ramp_bits=5 clk rst ctr.0 ctr.1 ctr.2 ctr.3 ctr.4
X0 ctr.0 1.0 NOT
X1 ctr.1 ctr.0 2 NAND
X2 2 3 NOT
X3 ctr.1 ctr.0 4 NOR
X4 4 3 1.1 NO…
ghost updated
8 years ago
-
There is a bug on the OpAmp from the Ideal library. See https://sourceforge.net/p/qucs/discussion/311050/thread/cccc70a5/
In the netlist line 5 it complains about the following:
```
R:R1 _net1 _net3…
-
Instances of some nets having RefDes and Pin swapped during parsing of the netlist