veripool verilog-perl issues

veripool / verilog-perl

Verilog parser, preprocessor, and related tools for the Verilog-Perl package

https://www.veripool.org/verilog-perl

Artistic License 2.0

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issues

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vhier - Apply skiplist to input files and module files as well

#1683 mksoc closed 4 weeks ago
2
contassign in interface causes missing method error in Verilog::Netlist

#1682 CoreyTeffetalor opened 3 months ago
1
surpress include file can't open error

#1681 riggy2013 closed 11 months ago
5
+define+ process function-like macros with errors.

#1680 elvenfarseer closed 1 year ago
1
Add a switch to ignore syntax error.

#1679 SimonZh1234 closed 1 year ago
1
Verilog::Preproc keeps comments containing word "module" although keep_comments=0

#1678 adrian1001 closed 1 year ago
2
need a parser for wire or reg signals

#1677 WilsonChen003 closed 1 year ago
2
Access package import declaration(s) after file parsing

#1676 fischphob opened 1 year ago
1
Change logic of t/03_spaces.t.

#1675 gregoa closed 2 years ago
2
parameter follows a '%' does not get replaced with obfuscated string

#1674 BlueStar-WhiteBirds closed 2 years ago
2
Add -MMD option

#1673 piecea opened 2 years ago
1
Vppreproc: MMD feature

#1672 piecea opened 2 years ago
1
Verilog::Getopt doesn't recognize ${ENVVAR} system environment variables

#1671 henry-hsieh closed 3 years ago
6
Failed to install Verilog::Language in Apple Mac Big Sur

#1670 Shang0801 opened 3 years ago
4
Parser didn't report macro with parsing library way

#1669 avendeng closed 3 years ago
3
Incorrect macro expansion with combination of `", ``, and embedded macro usage

#1668 martinwhitaker closed 3 years ago
5
`cpan install Verilog-Perl` seems to be broken

#1667 kevbroch closed 3 years ago
2
What happened to the Verilog-Perl forum content on veripool.org?

#1666 mpwalsh8 closed 4 years ago
1
Import statement script problem

#1665 PaulRolfe65 closed 4 years ago
5
How to prevent link errors on parameterised module instances using vhier?

#1664 sjalloq closed 4 years ago
2
Verilog-perl Parser test fails

#1663 ashfak12 closed 4 years ago
14
Question: AUTOINSTPARAM use with dependent parameters

#1662 veripoolbot closed 4 years ago
7
How is ppdefine in SigParser used

#1661 veripoolbot closed 4 years ago
4
Preprocessor doesn't handle one case of definition substitution properly

#1659 veripoolbot opened 4 years ago
2
Verilog::Preproc misdocuments def_exists instead of def_params

#1658 veripoolbot closed 4 years ago
4
Question: number of whitespaces between port name & signal name + indention + tabs replacement

#1611 veripoolbot closed 4 years ago
3
Getopt thinks a path is a comment

#1610 veripoolbot closed 4 years ago
4
Question: How to prevent AUTOOUTPUT from processing wires?

#1547 veripoolbot closed 4 years ago
1
perl 'make' commandline error during installation

#1546 veripoolbot closed 4 years ago
2
Question: not expose specific block parameter to the higher hierarchy level or expose it with its default value

#1501 veripoolbot closed 5 years ago
1
Verilog::Netlist::PinSelection->msb doesn't return anything.

#1500 veripoolbot closed 5 years ago
6
Verilog::Netlist::Cell->range doesn't return undef

#1497 veripoolbot closed 5 years ago
1
Question: Auto-indent inside macros systemverilog

#1464 veripoolbot closed 5 years ago
4
Vhier : Usage to display whole hierarchy of a pin or a port in a module or sub-module.

#1463 veripoolbot closed 5 years ago
1
Getting Error with Verilog::Netlist Module

#1459 veripoolbot closed 5 years ago
5
Question: Recursively reading files from verilog-library-flags

#1433 veripoolbot closed 5 years ago
3
Please add whatis entry in Netlist/PinSelection.pm

#1432 veripoolbot closed 5 years ago
3
Install problem from CPAN with 5.26.3/darwin-thread-multi-2level

#1428 veripoolbot closed 5 years ago
3
Question: how to split a port assignment to multiple lines?

#1421 veripoolbot closed 5 years ago
1
vrename --change misses escaped name if it is followed a newline for whitespace

#1420 veripoolbot closed 5 years ago
1
Question: Usage of '*' in verilog-library-directories

#1395 veripoolbot closed 5 years ago
1
Verilog::Std::std can return blank `std` package.

#1394 veripoolbot closed 5 years ago
2
Support ranged instances

#1393 veripoolbot closed 5 years ago
1
vhier --skiplist option not working

#1375 veripoolbot closed 5 years ago
1
vhier cannot find files in library

#1374 veripoolbot closed 5 years ago
1
Question: Indent after module open parenthesis with AUTOINST

#1345 veripoolbot closed 5 years ago
1
memory exhausted

#1344 veripoolbot closed 5 years ago
2
Constants split across lines

#1340 veripoolbot closed 6 years ago
5
Question: Using comments at end of line in AUTOINST

#1312 veripoolbot closed 6 years ago
3
Verilog::EditFiles misses module declarations where module keyword and module name are on separate lines

#1311 veripoolbot closed 6 years ago
1